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base repository: GlasgowEmbedded/glasgow
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head repository: GlasgowEmbedded/glasgow
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compare: 2520d9f4fe3d
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  • 1 commit
  • 5 files changed
  • 1 contributor

Commits on Apr 4, 2019

  1. fx2.FX2Arbiter→fx2_crossbar.FX2Crossbar 

    It's not so much an arbiter (there's only one bus master, the FPGA)
as a crossbar switch with an integrated control signal sequencer.
    @whitequark
    whitequark committed Apr 4, 2019
    Copy the full SHA
    2520d9f View commit details
22 changes: 11 additions & 11 deletions software/glasgow/access/direct/multiplexer.py
View file
Original file line number Diff line number Diff line change
@@ -68,14 +68,14 @@ def __init__(self, fifo):


class DirectMultiplexer(AccessMultiplexer):
def __init__(self, ports, pipes, registers, fx2_arbiter):
def __init__(self, ports, pipes, registers, fx2_crossbar):
self._ports = ports
self._claimed_ports = set()
self._pipes = pipes
self._claimed_pipes = 0
self._analyzer = None
self._registers = registers
self._fx2_arbiter = fx2_arbiter
self._fx2_crossbar = fx2_crossbar

def set_analyzer(self, analyzer):
assert self._analyzer is None
@@ -123,22 +123,22 @@ def claim_interface(self, applet, args, with_analyzer=True, throttle="fifo"):
self._pipes[pipe_num])

iface = DirectMultiplexerInterface(applet, analyzer, self._registers,
self._fx2_arbiter, pipe_num, pins, throttle)
self._fx2_crossbar, pipe_num, pins, throttle)
self.submodules += iface
return iface


class DirectMultiplexerInterface(AccessMultiplexerInterface):
def __init__(self, applet, analyzer, registers, fx2_arbiter, pipe_num, pins,
def __init__(self, applet, analyzer, registers, fx2_crossbar, pipe_num, pins,
throttle):
assert throttle in ("full", "fifo", "none")

super().__init__(applet, analyzer)
self._registers = registers
self._fx2_arbiter = fx2_arbiter
self._pipe_num = pipe_num
self._pins = pins
self._throttle = throttle
self._registers = registers
self._fx2_crossbar = fx2_crossbar
self._pipe_num = pipe_num
self._pins = pins
self._throttle = throttle

self.reset, self._addr_reset = self._registers.add_rw(1, reset=1)
self.logger.debug("adding reset register at address %#04x", self._addr_reset)
@@ -175,13 +175,13 @@ def _throttle_fifo(self, fifo):
return fifo

def get_in_fifo(self, **kwargs):
fifo = self._fx2_arbiter.get_in_fifo(self._pipe_num, **kwargs, reset=self.reset)
fifo = self._fx2_crossbar.get_in_fifo(self._pipe_num, **kwargs, reset=self.reset)
if self.analyzer:
self.analyzer.add_in_fifo_event(self.applet, fifo)
return self._throttle_fifo(_FIFOWritePort(fifo))

def get_out_fifo(self, **kwargs):
fifo = self._fx2_arbiter.get_out_fifo(self._pipe_num, **kwargs, reset=self.reset)
fifo = self._fx2_crossbar.get_out_fifo(self._pipe_num, **kwargs, reset=self.reset)
if self.analyzer:
self.analyzer.add_out_fifo_event(self.applet, fifo)
return self._throttle_fifo(_FIFOReadPort(fifo))
12 changes: 6 additions & 6 deletions software/glasgow/access/simulation/multiplexer.py
View file
Original file line number Diff line number Diff line change
@@ -2,7 +2,7 @@
from migen.genlib.fifo import _FIFOInterface, AsyncFIFO, SyncFIFOBuffered

from .. import AccessMultiplexer, AccessMultiplexerInterface
from ...gateware.fx2 import _FIFOWithFlush
from ...gateware.fx2_crossbar import _FIFOWithFlush


class SimulationMultiplexer(AccessMultiplexer):
@@ -30,15 +30,15 @@ def get_pin_name(self, pin):
def build_pin_tristate(self, pin, oe, o, i):
pass

def _make_fifo(self, arbiter_side, logic_side, cd_logic, depth, wrapper=lambda x: x):
def _make_fifo(self, crossbar_side, logic_side, cd_logic, depth, wrapper=lambda x: x):
if cd_logic is None:
fifo = wrapper(SyncFIFOBuffered(8, depth))
else:
assert isinstance(cd_logic, ClockDomain)

fifo = wrapper(ClockDomainsRenamer({
arbiter_side: "sys",
logic_side: "logic",
crossbar_side: "sys",
logic_side: "logic",
})(AsyncFIFO(8, depth)))

fifo.clock_domains.cd_logic = ClockDomain()
@@ -52,7 +52,7 @@ def get_in_fifo(self, depth=512, auto_flush=False, clock_domain=None):
assert self.in_fifo is None

self.submodules.in_fifo = self._make_fifo(
arbiter_side="read", logic_side="write", cd_logic=clock_domain, depth=depth,
crossbar_side="read", logic_side="write", cd_logic=clock_domain, depth=depth,
wrapper=lambda x: _FIFOWithFlush(x, asynchronous=clock_domain is not None,
auto_flush=auto_flush))
return self.in_fifo
@@ -61,7 +61,7 @@ def get_out_fifo(self, depth=512, clock_domain=None):
assert self.out_fifo is None

self.submodules.out_fifo = self._make_fifo(
arbiter_side="write", logic_side="read", cd_logic=clock_domain, depth=depth)
crossbar_side="write", logic_side="read", cd_logic=clock_domain, depth=depth)
return self.out_fifo

def get_inout_fifo(self, **kwargs):
4 changes: 2 additions & 2 deletions software/glasgow/applet/audio/yamaha_opl/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -797,8 +797,8 @@ def build(self, target, args):
self.mux_interface = iface = target.multiplexer.claim_interface(self, args)
subtarget = iface.add_subtarget(YamahaOPxSubtarget(
pads=iface.get_pads(args, pins=self.__pins, pin_sets=self.__pin_sets),
# These FIFO depths are somewhat dependent on the (current, bad) arbiter in Glasgow,
# but they work for now. With a better arbiter they should barely matter.
# These FIFO depths are somewhat dependent on the (current, bad) crossbar in Glasgow,
# but they work for now. With a better crossbar they should barely matter.
out_fifo=iface.get_out_fifo(depth=512),
in_fifo=iface.get_in_fifo(depth=8192, auto_flush=False),
# It's useful to run the synthesizer at a frequency significantly higher than real-time
24 changes: 12 additions & 12 deletions software/glasgow/gateware/fx2.py → software/glasgow/gateware/fx2_crossbar.py
View file
Original file line number Diff line number Diff line change
@@ -29,7 +29,7 @@
from migen.genlib.resetsync import AsyncResetSynchronizer


__all__ = ["FX2Arbiter"]
__all__ = ["FX2Crossbar"]


class _DummyFIFO(Module, _FIFOInterface):
@@ -154,13 +154,13 @@ def __init__(self, pads):
self.submodules.pktend_t = _RegisteredTristate(pads.pktend)


class FX2Arbiter(Module):
class FX2Crossbar(Module):
"""
FX2 FIFO bus master.
Shuttles data between FX2 and FIFOs in bursts.
The arbiter supports up to four FIFOs organized as ``OUT, OUT, IN, IN``.
The crossbar supports up to four FIFOs organized as ``OUT, OUT, IN, IN``.
FIFOs that are never requested are not implemented and behave as if they
are never readable or writable.
"""
@@ -309,7 +309,7 @@ def do_finalize(self):
)
)

def _make_fifo(self, arbiter_side, logic_side, cd_logic, reset, depth, wrapper):
def _make_fifo(self, crossbar_side, logic_side, cd_logic, reset, depth, wrapper):
if cd_logic is None:
fifo = wrapper(SyncFIFOBuffered(8, depth))

@@ -320,8 +320,8 @@ def _make_fifo(self, arbiter_side, logic_side, cd_logic, reset, depth, wrapper):
assert isinstance(cd_logic, ClockDomain)

fifo = wrapper(ClockDomainsRenamer({
arbiter_side: "arbiter",
logic_side: "logic",
crossbar_side: "crossbar",
logic_side: "logic",
})(AsyncFIFO(8, depth)))

# Note that for the reset to get asserted AND deasserted, the logic clock domain must
@@ -336,14 +336,14 @@ def _make_fifo(self, arbiter_side, logic_side, cd_logic, reset, depth, wrapper):
# This can lead to all sorts of framing issues, and is rather unfortunate, but at
# the moment I do not know of a way to fix this, since Migen does not support
# asynchronous resets.
fifo.clock_domains.cd_arbiter = ClockDomain(reset_less=reset is None)
fifo.clock_domains.cd_logic = ClockDomain(reset_less=reset is None)
fifo.clock_domains.cd_crossbar = ClockDomain(reset_less=reset is None)
fifo.clock_domains.cd_logic = ClockDomain(reset_less=reset is None)
fifo.comb += [
fifo.cd_arbiter.clk.eq(ClockSignal()),
fifo.cd_crossbar.clk.eq(ClockSignal()),
fifo.cd_logic.clk.eq(cd_logic.clk),
]
if reset is not None:
fifo.comb += fifo.cd_arbiter.rst.eq(reset)
fifo.comb += fifo.cd_crossbar.rst.eq(reset)
fifo.specials += AsyncResetSynchronizer(fifo.cd_logic, reset)

self.submodules += fifo
@@ -353,7 +353,7 @@ def get_out_fifo(self, n, depth=512, clock_domain=None, reset=None):
assert 0 <= n < 2
assert isinstance(self.out_fifos[n].fifo, _DummyFIFO)

fifo = self._make_fifo(arbiter_side="write",
fifo = self._make_fifo(crossbar_side="write",
logic_side="read",
cd_logic=clock_domain,
reset=reset,
@@ -366,7 +366,7 @@ def get_in_fifo(self, n, depth=512, auto_flush=True, clock_domain=None, reset=No
assert 0 <= n < 2
assert isinstance(self.in_fifos[n].fifo, _DummyFIFO)

fifo = self._make_fifo(arbiter_side="read",
fifo = self._make_fifo(crossbar_side="read",
logic_side="write",
cd_logic=clock_domain,
reset=reset,
6 changes: 3 additions & 3 deletions software/glasgow/target/hardware.py
View file
Original file line number Diff line number Diff line change
@@ -10,7 +10,7 @@
from ..gateware.pads import Pads
from ..gateware.i2c import I2CSlave
from ..gateware.registers import I2CRegisters
from ..gateware.fx2 import FX2Arbiter
from ..gateware.fx2_crossbar import FX2Crossbar
from ..gateware.platform.lattice import special_overrides
from ..platform import GlasgowPlatformRevAB, GlasgowPlatformRevC0
from .analyzer import GlasgowAnalyzer
@@ -71,7 +71,7 @@ def __init__(self, revision, multiplexer_cls=None, with_analyzer=False):
self.submodules.registers = I2CRegisters(self.i2c_slave)
self.comb += self.i2c_slave.address.eq(0b0001000)

self.submodules.fx2_arbiter = FX2Arbiter(self.platform.request("fx2"))
self.submodules.fx2_crossbar = FX2Crossbar(self.platform.request("fx2"))

self.ports = {
"A": (8, lambda n: self.platform.request("port_a", n)),
@@ -81,7 +81,7 @@ def __init__(self, revision, multiplexer_cls=None, with_analyzer=False):
if multiplexer_cls:
pipes = "PQ"
self.submodules.multiplexer = multiplexer_cls(ports=self.ports, pipes="PQ",
registers=self.registers, fx2_arbiter=self.fx2_arbiter)
registers=self.registers, fx2_crossbar=self.fx2_crossbar)
else:
self.multiplexer = None