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base repository: GlasgowEmbedded/glasgow
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base: c5816569a926
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head repository: GlasgowEmbedded/glasgow
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compare: c733acea0456
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Apr 6, 2019

  1. support.bits: fix misleading error message.

    @whitequark
    whitequark committed Apr 6, 2019
    Copy the full SHA
    c733ace View commit details
Showing with 8 additions and 8 deletions.
  1. +8 −8 software/glasgow/support/bits.py
16 changes: 8 additions & 8 deletions software/glasgow/support/bits.py
View file
Original file line number Diff line number Diff line change
@@ -33,14 +33,14 @@ def _check_integer(action, expected_width, value):
% (action, expected_width, value.bit_length(), value))

@classmethod
def _define_fields(cls, size_bits, fields):
total_width = sum(width for name, width in fields)
if total_width != size_bits:
raise TypeError("declared total width is %d bits, but sum of field widths is %d bits"
% (total_width, size_bits))

cls._size_bits = size_bits
cls._size_bytes = (size_bits + 7) // 8
def _define_fields(cls, declared_bits, fields):
total_bits = sum(width for name, width in fields)
if total_bits != declared_bits:
raise TypeError("declared width is %d bits, but sum of field widths is %d bits"
% (declared_bits, total_bits))

cls._size_bits = declared_bits
cls._size_bytes = (declared_bits + 7) // 8
cls._named_fields = []
cls._widths = OrderedDict()