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base repository: GlasgowEmbedded/glasgow
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head repository: GlasgowEmbedded/glasgow
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compare: 42cb99d9c056
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  • 3 commits
  • 2 files changed
  • 1 contributor

Commits on Apr 5, 2019

  1. support.logging: dump_hex: show total bytes, not elided bytes. 

    It's not actually clear how many bytes are shown, so printing how
many bytes are elided isn't helpful at all. Instead, print the total
count, which is handy e.g. to see if a complete packet was received.
    @whitequark
    whitequark committed Apr 5, 2019
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    79e038c View commit details

  2. applet.memory.onfi: explicitly flush IN FIFO. 

    Improves throughput.
    @whitequark
    whitequark committed Apr 5, 2019
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    82b391b View commit details

  3. applet.memory.onfi: elide hex dumps from logs. 

    Improves throughput by avoiding converting to hex the data that will
never get actually shown, and makes logs more readable.
    @whitequark
    whitequark committed Apr 5, 2019
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    42cb99d View commit details
Showing with 10 additions and 8 deletions.
  1. +8 −6 software/glasgow/applet/memory/onfi/__init__.py
  2. +2 −2 software/glasgow/support/logging.py
14 changes: 8 additions & 6 deletions software/glasgow/applet/memory/onfi/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -6,6 +6,7 @@
from migen.genlib.cdc import MultiReg

from ....support.pyrepl import *
from ....support.logging import *
from ....database.jedec import *
from ... import *

@@ -68,7 +69,7 @@ def __init__(self, pads, in_fifo, out_fifo):

self.submodules.fsm = FSM(reset_state="RECV-COMMAND")
self.fsm.act("RECV-COMMAND",
NextValue(bus.doe, 0),
in_fifo.flush.eq(1),
If(out_fifo.readable,
out_fifo.re.eq(1),
NextValue(command, out_fifo.dout),
@@ -79,7 +80,8 @@ def __init__(self, pads, in_fifo, out_fifo):
).Elif((out_fifo.dout == CMD_WAIT),
NextState("ONFI-SETUP")
)
)
),
NextValue(bus.doe, 0)
)
self.fsm.act("RECV-CONTROL",
If(out_fifo.readable,
@@ -219,14 +221,14 @@ async def _do(self, command, address=[], wait=False):
async def _do_write(self, command, address=[], wait=False, data=[]):
data = bytes(data)
await self._do(command, address, wait)
self._log("write data=<%s>", data.hex())
self._log("write data=<%s>", dump_hex(data))
await self._write(data)

async def _do_read(self, command, address=[], wait=False, length=0):
await self._do(command, address, wait)
await self._read(length)
data = await self.lower.read(length)
self._log("read data=<%s>", data.hex())
self._log("read data=<%s>", dump_hex(data))
return data

async def reset(self):
@@ -285,7 +287,7 @@ async def program(self, row, chunks):

for (column, data) in chunks:
data = bytes(data)
self._log("column=%#06x data=<%s>", column, data.hex())
self._log("column=%#06x data=<%s>", column, dump_hex(data))
await self._do_write(command=0x85, address=[
(column >> 0) & 0xff,
(column >> 8) & 0xff,
@@ -348,7 +350,7 @@ def build(self, target, args):
self.mux_interface = iface = target.multiplexer.claim_interface(self, args)
iface.add_subtarget(MemoryONFISubtarget(
pads=iface.get_pads(args, pin_sets=self.pin_sets, pins=self.pins),
in_fifo=iface.get_in_fifo(),
in_fifo=iface.get_in_fifo(auto_flush=False),
out_fifo=iface.get_out_fifo(),
))

4 changes: 2 additions & 2 deletions software/glasgow/support/logging.py
View file
Original file line number Diff line number Diff line change
@@ -10,8 +10,8 @@ def to_hex(data):
if dump_hex.limit == 0 or len(data) < dump_hex.limit:
return data.hex()
else:
return "{}... ({} more bytes)".format(
data[:dump_hex.limit].hex(), len(data) - dump_hex.limit)
return "{}... ({} bytes total)".format(
data[:dump_hex.limit].hex(), len(data))
except AttributeError:
return to_hex(bytes(data))
return lazy(lambda: to_hex(data))