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build.plat: add iter_extra_files method.
* vendor.xilinx_7series: employ iter_extra_files.
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@@ -55,17 +55,13 @@ class Xilinx7SeriesPlatform(TemplatedPlatform): | |
"{{name}}.tcl": r""" | ||
# {{autogenerated}} | ||
create_project -force -name {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}} | ||
{% for file in platform.extra_files %} | ||
{% if file.endswith((".v", ".sv")) -%} | ||
add_files {{file}} | ||
{% endif %} | ||
{% for file in platform.iter_extra_files(".v", ".sv") %} | ||
add_files {{file}} | ||
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whitequark
Contributor
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{% endfor %} | ||
add_files {{name}}.v | ||
read_xdc {{name}}.xdc | ||
{% for file in platform.extra_files %} | ||
{% if file.endswith("xdc") -%} | ||
read_xdc {{file}} | ||
{% endif %} | ||
{% for file in platform.iter_extra_files(".xdc") %} | ||
read_xdc {{file}} | ||
{% endfor %} | ||
{{get_override("script_after_read")|default("# (script_after_read placeholder)")}} | ||
synth_design -top {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}} | ||
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This isn't important at all, but Python allows doing this a bit more elegantly if you want a generator anyway: