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base repository: whitequark/Boneless-CPU
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head repository: whitequark/Boneless-CPU
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compare: cec7304f51a3
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Jul 1, 2019

  1. gateware.alsru: update for newer nMigen.

    @whitequark
    whitequark committed Jul 1, 2019
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    b1bbd18 View commit details

  2. gateware.alsru: style. NFC.

    @whitequark
    whitequark committed Jul 1, 2019
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    cec7304 View commit details
Showing with 9 additions and 11 deletions.
  1. +9 −11 boneless/gateware/alsru.py
20 changes: 9 additions & 11 deletions boneless/gateware/alsru.py
View file
Original file line number Diff line number Diff line change
@@ -8,8 +8,7 @@ class ALSRU:
"""Arithmetical, logical, shift, and rotate unit."""

# defined by subclasses
CTRL_BITS = None

BITS_OP = None
CTRL_A = None
CTRL_B = None
CTRL_nB = None
@@ -58,10 +57,10 @@ def ctrl_decoder(cls, word):
return "R<<1"
if word == cls.CTRL_SR._as_const():
return "R>>1"
return "? {:0{}b}".format(word, cls.CTRL_BITS)
return "? {:0{}b}".format(word, cls.BITS_OP)


class ALSRU_4LUT(ALSRU):
class ALSRU_4LUT(ALSRU, Elaboratable):
"""ALSRU optimized for 4-LUT architecture with no adder pre-inversion.
On iCE40 with Yosys, ABC, and -relut this synthesizes to the optimal 4n+3 LUTs.
@@ -100,10 +99,10 @@ class ALSRU_4LUT(ALSRU):
MUX_S_R = 0b1

MUX_X_x = 0
MUX_X_AaB = 0b00
MUX_X_AoB = 0b01
MUX_X_AxB = 0b10
MUX_X_A = 0b11
MUX_X_A = 0b00
MUX_X_AaB = 0b01
MUX_X_AoB = 0b10
MUX_X_AxB = 0b11

MUX_Y_0 = 0b00
MUX_Y_S = 0b01
@@ -113,8 +112,7 @@ class ALSRU_4LUT(ALSRU):
MUX_O_XpY = 0b0
MUX_O_Y = 0b1

CTRL_BITS = 6

BITS_OP = 6
CTRL_A = Cat(C(MUX_S_x, 1), C(MUX_X_A, 2), C(MUX_Y_0, 2), C(MUX_O_XpY, 1))
CTRL_B = Cat(C(MUX_S_x, 1), C(MUX_X_x, 2), C(MUX_Y_B, 2), C(MUX_O_Y, 1))
CTRL_nB = Cat(C(MUX_S_x, 1), C(MUX_X_x, 2), C(MUX_Y_nB, 2), C(MUX_O_Y, 1))
@@ -189,7 +187,7 @@ def elaborate(self, platform):

m.d.sync += self.r.eq(self.o)

return m.lower(platform)
return m

# -------------------------------------------------------------------------------------------------