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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 7cc0b8cbf00c
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Jul 2, 2019

  1. hdl.mem: fix naming of registers inside unnamed memories.

    Before this commit, `None` would leak into the vcd file with pysim.
    whitequark committed Jul 2, 2019
    Copy the full SHA
    7cc0b8c View commit details
Showing with 2 additions and 1 deletion.
  1. +2 −1 nmigen/hdl/mem.py
3 changes: 2 additions & 1 deletion nmigen/hdl/mem.py
Original file line number Diff line number Diff line change
@@ -27,7 +27,8 @@ def __init__(self, width, depth, init=None, name=None, simulate=True):
self._array = Array()
if simulate:
for addr in range(self.depth):
self._array.append(Signal(self.width, name="{}({})".format(name, addr)))
self._array.append(Signal(self.width, name="{}({})"
.format(name or "memory", addr)))

self.init = init