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base repository: m-labs/nmigen
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base: 0ab215e5ed76
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head repository: m-labs/nmigen
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compare: 9a1048af50aa
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Jul 3, 2019

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    9a1048a View commit details
Showing with 1 addition and 1 deletion.
  1. +1 −1 nmigen/vendor/lattice_ecp5.py
2 changes: 1 addition & 1 deletion nmigen/vendor/lattice_ecp5.py
Original file line number Diff line number Diff line change
@@ -259,7 +259,7 @@ def get_input(self, pin, port, attrs, invert):
self._check_feature("single-ended input", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
m = Module()
t, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
for bit in range(len(port)):
m.submodules += Instance("IB",
i_I=port[bit],