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Unable to create a ring oscillator #118
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@DurandA did you forgot to assign |
m.d.comb += buffers_in.eq(buffers_out[-1:] + buffers_out[0:-1]) should spell m.d.comb += buffers_in.eq(Cat(buffer_out[-1], buffers_out[:-1])) to reflect the Verilog code assign buffers_in = {buffers_out[5:0], buffers_out[6]}; |
Many thanks, this solved the issue. I thought that Python slices supported concatenation. |
Python doesn't have a slice object*, it has a slice operator. The slice operator applied to lists returns a list, and list's * There is the |
Thank you for the clarification! This is very much appreciated. |
I am trying to build a ring oscillator (targeting iCE40) using nmigen. I first made a simple Verilog design (see above, adapted from Clifford's ringosc.v) and then tried to port it to nmigen:
Unfortunately, the above code doesn't produce a working oscillator. It is unclear to me if I don't understand how to use nmigen clocks or if this is due to unwanted optimizations (or if I made a dumb mistake somewhere else).
Here is a simple working version in Verilog:
For both versions, nextpnr should be configured with
--ignore-loops
switch.How to use a proper clock attached to the oscillator? Is this problem related to #57?
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