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base repository: m-labs/nmigen
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compare: 20553b1478f0
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  • 1 commit
  • 5 files changed
  • 1 contributor

Commits on Jul 2, 2019

  1. build.plat: add iter_extra_files method.

    * vendor.*: employ iter_extra_files.
    peteut authored and whitequark committed Jul 2, 2019
    Copy the full SHA
    20553b1 View commit details
Showing with 19 additions and 24 deletions.
  1. +3 −0 nmigen/build/plat.py
  2. +5 −6 nmigen/vendor/lattice_ecp5.py
  3. +5 −6 nmigen/vendor/lattice_ice40.py
  4. +4 −8 nmigen/vendor/xilinx_7series.py
  5. +2 −4 nmigen/vendor/xilinx_spartan6.py
3 changes: 3 additions & 0 deletions nmigen/build/plat.py
Original file line number Diff line number Diff line change
@@ -281,3 +281,6 @@ def render(source, origin):
for filename, content in self.extra_files.items():
plan.add_file(filename, content)
return plan

def iter_extra_files(self, *endswith):
return (f for f in self.extra_files if f.endswith(endswith))
11 changes: 5 additions & 6 deletions nmigen/vendor/lattice_ecp5.py
Original file line number Diff line number Diff line change
@@ -67,12 +67,11 @@ class LatticeECP5Platform(TemplatedPlatform):
""",
"{{name}}.ys": r"""
# {{autogenerated}}
{% for file in platform.extra_files %}
{% if file.endswith(".v") -%}
read_verilog {{get_override("read_opts")|join(" ")}} {{file}}
{% elif file.endswith(".sv") -%}
read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}}
{% endif %}
{% for file in platform.iter_extra_files(".v") -%}
read_verilog {{get_override("read_opts")|join(" ")}} {{file}}
{% endfor %}
{% for file in platform.iter_extra_files(".sv") -%}
read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}}
{% endfor %}
read_ilang {{name}}.il
{{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
11 changes: 5 additions & 6 deletions nmigen/vendor/lattice_ice40.py
Original file line number Diff line number Diff line change
@@ -59,12 +59,11 @@ class LatticeICE40Platform(TemplatedPlatform):
""",
"{{name}}.ys": r"""
# {{autogenerated}}
{% for file in platform.extra_files %}
{% if file.endswith(".v") -%}
read_verilog {{get_override("read_opts")|join(" ")}} {{file}}
{% elif file.endswith(".sv") -%}
read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}}
{% endif %}
{% for file in platform.iter_extra_files(".v") -%}
read_verilog {{get_override("read_opts")|join(" ")}} {{file}}
{% endfor %}
{% for file in platform.iter_extra_files(".sv") -%}
read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}}
{% endfor %}
read_ilang {{name}}.il
{{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
12 changes: 4 additions & 8 deletions nmigen/vendor/xilinx_7series.py
Original file line number Diff line number Diff line change
@@ -55,17 +55,13 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
"{{name}}.tcl": r"""
# {{autogenerated}}
create_project -force -name {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}}
{% for file in platform.extra_files %}
{% if file.endswith((".v", ".sv")) -%}
add_files {{file}}
{% endif %}
{% for file in platform.iter_extra_files(".v", ".sv") -%}
add_files {{file}}
{% endfor %}
add_files {{name}}.v
read_xdc {{name}}.xdc
{% for file in platform.extra_files %}
{% if file.endswith("xdc") -%}
read_xdc {{file}}
{% endif %}
{% for file in platform.iter_extra_files(".xdc") -%}
read_xdc {{file}}
{% endfor %}
{{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
synth_design -top {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}}
6 changes: 2 additions & 4 deletions nmigen/vendor/xilinx_spartan6.py
Original file line number Diff line number Diff line change
@@ -57,10 +57,8 @@ class XilinxSpartan6Platform(TemplatedPlatform):
""",
"{{name}}.prj": r"""
# {{autogenerated}}
{% for file in platform.extra_files -%}
{% if file.endswith(".v") %}
verilog work {{file}}
{% endif %}
{% for file in platform.iter_extra_files(".v") -%}
verilog work {{file}}
{% endfor %}
verilog work {{name}}.v
""",