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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
compare: 34a97b27512a
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Aug 4, 2019

  1. back.rtlil: use a dummy wire, not 'x, when assigning to shorter LHS. 

    Using 'x is legal RTLIL, in theory, but in practice it crashes Yosys
and when it doesn't, it causes Yosys to produce invalid Verilog.
Using a dummy wire is always safe and is not a major readability
issue as this is a rare corner case.

(It is not trivial to shorten the RHS in this case, because during
expansion of an ArrayProxy, match_shape() could be called in
a context far from the RHS handling logic.)
    whitequark committed Aug 4, 2019
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  2. vendor.lattice_ice40: avoid routing conflicts with SDR/DDR input pins.

    whitequark committed Aug 4, 2019
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