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base repository: m-labs/nmigen
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compare: 34a97b27512a
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Aug 4, 2019

  1. back.rtlil: use a dummy wire, not 'x, when assigning to shorter LHS.

    Using 'x is legal RTLIL, in theory, but in practice it crashes Yosys
    and when it doesn't, it causes Yosys to produce invalid Verilog.
    Using a dummy wire is always safe and is not a major readability
    issue as this is a rare corner case.
    
    (It is not trivial to shorten the RHS in this case, because during
    expansion of an ArrayProxy, match_shape() could be called in
    a context far from the RHS handling logic.)
    whitequark committed Aug 4, 2019
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    2e6627c View commit details
  2. Copy the full SHA
    34a97b2 View commit details
Showing with 8 additions and 4 deletions.
  1. +2 −2 nmigen/back/rtlil.py
  2. +6 −2 nmigen/vendor/lattice_ice40.py
4 changes: 2 additions & 2 deletions nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
@@ -578,9 +578,9 @@ def match_shape(self, value, new_bits, new_sign):
elif new_bits < value_bits:
return self(ast.Slice(value, 0, new_bits))
else: # new_bits > value_bits
# It is legal to assign to constants on LHS in RTLIL; such assignments are ignored.
dummy_bits = new_bits - value_bits
return "{{ {}'{} {} }}".format(dummy_bits, "x" * dummy_bits, self(value))
dummy_wire = self.s.rtlil.wire(dummy_bits)
return "{{ {} {} }}".format(dummy_wire, self(value))

def on_Signal(self, value):
if value not in self.s.driven:
8 changes: 6 additions & 2 deletions nmigen/vendor/lattice_ice40.py
Original file line number Diff line number Diff line change
@@ -244,11 +244,15 @@ def get_oxor(a, invert):
]

if "i" not in pin.dir:
i_type = 0b00 # PIN_NO_INPUT aka PIN_INPUT_REGISTERED
# If no input pin is requested, it is important to use a non-registered input pin
# type, because an output-only pin would not have an input clock, and if its input
# is configured as registered, this would prevent a co-located input-capable pin
# from using an input clock.
i_type = 0b01 # PIN_INPUT
elif pin.xdr == 0:
i_type = 0b01 # PIN_INPUT
elif pin.xdr > 0:
i_type = 0b00 # PIN_INPUT_REGISTERED
i_type = 0b00 # PIN_INPUT_REGISTERED aka PIN_INPUT_DDR
if "o" not in pin.dir:
o_type = 0b0000 # PIN_NO_OUTPUT
elif pin.xdr == 0 and pin.dir == "o":