Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/nmigen-boards
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 6fd7735f77b9
Choose a base ref
...
head repository: m-labs/nmigen-boards
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 0ddf31787e22
Choose a head ref
  • 2 commits
  • 7 files changed
  • 1 contributor

Commits on Aug 4, 2019

  1. Add missing trailing spaces to multiline connector definitions.

    Or the last and the first on line pin get glued together.
    whitequark committed Aug 4, 2019
    Copy the full SHA
    209f84e View commit details
  2. [breaking-change] Factor out "sram" resource.

    Fixes #9.
    whitequark committed Aug 4, 2019
    Copy the full SHA
    0ddf317 View commit details
Showing with 54 additions and 50 deletions.
  1. +5 −13 nmigen_boards/blackice.py
  2. +6 −15 nmigen_boards/blackice_ii.py
  3. +1 −0 nmigen_boards/dev/__init__.py
  4. +18 −0 nmigen_boards/dev/sram.py
  5. +16 −16 nmigen_boards/ice40_hx8k_b_evn.py
  6. +2 −2 nmigen_boards/icebreaker.py
  7. +6 −4 nmigen_boards/tinyfpga_bx.py
18 changes: 5 additions & 13 deletions nmigen_boards/blackice.py
Original file line number Diff line number Diff line change
@@ -41,19 +41,11 @@ class BlackIcePlatform(LatticeICE40Platform):
attrs=Attrs(IO_STANDARD="SB_LVCMOS33", PULLUP="1")
),

Resource("sram", 0,
Subsignal("address", Pins(
"137 138 139 141 142 42 43 44 73 74 75 76 115 116 117 118 119 78",
dir="o"
)),
Subsignal("data", Pins(
"135 134 130 128 125 124 122 121 61 60 56 55 52 49 48 47",
dir="io"
)),
Subsignal("oe", PinsN("45", dir="o")),
Subsignal("we", PinsN("120", dir="o")),
Subsignal("cs", PinsN("136", dir="o")),
Attrs(IO_STANDARD="SB_LVCMOS33"),
SRAMResource(0,
cs="136", oe="45", we="120",
a="137 138 139 141 142 42 43 44 73 74 75 76 115 116 117 118 119 78",
d="135 134 130 128 125 124 122 121 61 60 56 55 52 49 48 47",
attrs=Attrs(IO_STANDARD="SB_LVCMOS33"),
),
]
connectors = [
21 changes: 6 additions & 15 deletions nmigen_boards/blackice_ii.py
Original file line number Diff line number Diff line change
@@ -41,21 +41,12 @@ class BlackIceIIPlatform(LatticeICE40Platform):
attrs=Attrs(IO_STANDARD="SB_LVCMOS33", PULLUP="1")
),

Resource("sram", 0,
Subsignal("address", Pins(
"137 138 139 141 142 42 43 44 73 74 75 76 115 116 117 118 119 78",
dir="o"
)),
Subsignal("data", Pins(
"136 135 134 130 125 124 122 121 62 61 60 56 55 48 47 45",
dir="io"
)),
Subsignal("oe", PinsN("29", dir="o")),
Subsignal("we", PinsN("120", dir="o")),
Subsignal("cs", PinsN("136", dir="o")),
Subsignal("ub", PinsN("28", dir="o")),
Subsignal("lb", PinsN("24", dir="o")),
Attrs(IO_STANDARD="SB_LVCMOS33"),
SRAMResource(0,
cs="136", oe="29", we="120",
a="137 138 139 141 142 42 43 44 73 74 75 76 115 116 117 118 119 78",
d="136 135 134 130 125 124 122 121 62 61 60 56 55 48 47 45",
dm="24 28",
attrs=Attrs(IO_STANDARD="SB_LVCMOS33"),
),
]
connectors = [
1 change: 1 addition & 0 deletions nmigen_boards/dev/__init__.py
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
from .uart import UARTResource
from .flash import SPIFlashResources
from .spi import SPIResource
from .sram import SRAMResource
18 changes: 18 additions & 0 deletions nmigen_boards/dev/sram.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,18 @@
from nmigen.build import *


__all__ = ["SRAMResource"]


def SRAMResource(*args, cs, oe, we, a, d, dm=None, attrs=None):
io = []
io.append(Subsignal("cs", PinsN(cs, dir="o")))
io.append(Subsignal("oe", PinsN(oe, dir="o")))
io.append(Subsignal("we", PinsN(we, dir="o")))
io.append(Subsignal("a", Pins(a, dir="o")))
io.append(Subsignal("d", Pins(d, dir="io")))
if dm is not None:
io.append(Subsignal("dm", PinsN(dm, dir="o"))) # dm="LB# UB#"
if attrs is not None:
io.append(attrs)
return Resource.family(*args, default_name="sram", ios=io)
32 changes: 16 additions & 16 deletions nmigen_boards/ice40_hx8k_b_evn.py
Original file line number Diff line number Diff line change
@@ -38,25 +38,25 @@ class ICE40HX8KBEVNPlatform(LatticeICE40Platform):
]
connectors = [
Connector("j", 1, # J1
"A16 - A15 B15 B13 B14 - - B12 B11"
"A11 B10 A10 C9 - - A9 B9 B8 A7"
"B7 C7 - - A6 C6 B6 C5 A5 C4"
"- - B5 C3 B4 B3 A2 A1 - -"),
"A16 - A15 B15 B13 B14 - - B12 B11 "
"A11 B10 A10 C9 - - A9 B9 B8 A7 "
"B7 C7 - - A6 C6 B6 C5 A5 C4 "
"- - B5 C3 B4 B3 A2 A1 - - "),
Connector("j", 2, # J2
"- - - R15 P16 P15 - - N16 M15"
"M16 L16 K15 K16 - - K14 J14 G14 F14"
"J15 H14 - - H16 G15 G16 F15 F16 E14"
"- - E16 D15 D16 D14 C16 B16 - -"),
"- - - R15 P16 P15 - - N16 M15 "
"M16 L16 K15 K16 - - K14 J14 G14 F14 "
"J15 H14 - - H16 G15 G16 F15 F16 E14 "
"- - E16 D15 D16 D14 C16 B16 - - "),
Connector("j", 3, # J3
"R16 - T15 T16 T13 T14 - - N12 P13"
"N10 M11 T11 P10 - - T10 R10 P8 P9"
"T9 R9 - - T7 T8 T6 R6 T5 R5"
"- - R3 R4 R2 T3 T1 T2 - -"),
"R16 - T15 T16 T13 T14 - - N12 P13 "
"N10 M11 T11 P10 - - T10 R10 P8 P9 "
"T9 R9 - - T7 T8 T6 R6 T5 R5 "
"- - R3 R4 R2 T3 T1 T2 - - "),
Connector("j", 4, # J4
"- - - R1 P1 P2 - - N3 N2"
"M2 M1 L3 L1 - - K3 K1 J2 J1"
"H2 J3 - - G2 H1 F2 G1 E2 F1"
"- - D1 D2 C1 C2 B1 B2 - -"),
"- - - R1 P1 P2 - - N3 N2 "
"M2 M1 L3 L1 - - K3 K1 J2 J1 "
"H2 J3 - - G2 H1 F2 G1 E2 F1 "
"- - D1 D2 C1 C2 B1 B2 - - "),
]

def toolchain_program(self, products, name):
4 changes: 2 additions & 2 deletions nmigen_boards/icebreaker.py
Original file line number Diff line number Diff line change
@@ -36,9 +36,9 @@ class ICEBreakerPlatform(LatticeICE40Platform):
),
]
connectors = [
Connector("pmod", 0, "4 2 47 45 - - 3 48 46 44 - -"), # PMOD1A
Connector("pmod", 0, " 4 2 47 45 - - 3 48 46 44 - -"), # PMOD1A
Connector("pmod", 1, "43 38 34 31 - - 42 36 32 28 - -"), # PMOD1B
Connector("pmod", 2, "27 25 21 19 - - 26 23 20 18 - -"), # PMOD2
Connector("pmod", 2, "27 25 21 19 - - 26 23 20 18 - -"), # PMOD2
]
# The attached LED/button section can be either used standalone or as a PMOD.
# Attach to platform using:
10 changes: 6 additions & 4 deletions nmigen_boards/tinyfpga_bx.py
Original file line number Diff line number Diff line change
@@ -28,19 +28,21 @@ class TinyFPGABXPlatform(LatticeICE40Platform):

*SPIFlashResources(0,
cs="F7", clk="G7", mosi="G6", miso="H7", wp="H4", hold="J8",
attrs=Attrs(IO_STANDARD="SB_LVCMOS33")),
attrs=Attrs(IO_STANDARD="SB_LVCMOS33")
),
]
connectors = [
Connector("gpio", 0,
# Left side of the board
# 1 2 3 4 5 6 7 8 9 10 11 12 13
" A2 A1 B1 C2 C1 D2 D1 E2 E1 G2 H1 J1 H2"
" A2 A1 B1 C2 C1 D2 D1 E2 E1 G2 H1 J1 H2 "
# Right side of the board
# 14 15 16 17 18 19 20 21 22 23 24
" H9 D9 D8 B8 A9 B8 A8 B7 A7 B6 A6"
" H9 D9 D8 B8 A9 B8 A8 B7 A7 B6 A6 "
# Bottom of the board
# 25 26 27 28 29 30 31
"G1 J3 J4 G9 J9 E8 J2"),
"G1 J3 J4 G9 J9 E8 J2"
),
]

def toolchain_program(self, products, name):