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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 99d205494a89
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- 4 commits
- 9 files changed
- 1 contributor
Commits on Aug 3, 2019
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hdl.ir: don't expose as ports missing domains added via elaboratables.
The elaboratable is already likely driving the clk/rst signals in some way appropriate for the platform; if we expose them as ports nevertheless it will cause problems downstream.
whitequark committedAug 3, 2019 Configuration menu - View commit details
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hdl.ir: allow adding more than one domain in missing domain callback.
This is useful for injecting complex power-on reset logic.
whitequark committedAug 3, 2019 Configuration menu - View commit details
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build.plat,vendor: automatically create sync domain from default_clk.
But only if it is not defined by the programmer. Closes #57.
whitequark committedAug 3, 2019 Configuration menu - View commit details
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hdl.dsl: reword m.If(~True) warning to be more clear.
Before this commit, it only suggested one thing (silencing it) and that's wrong almost all of the time, so suggest the right thing instead.
whitequark committedAug 3, 2019 Configuration menu - View commit details
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