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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: d0ac8bf78940
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Aug 3, 2019

  1. back.rtlil: actually match shape of left hand side.

    This comes up in code such as:
      Array([Signal(1), Signal(8)]).eq(Const(0, 8))
    whitequark committed Aug 3, 2019
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    d0ac8bf View commit details
Showing with 9 additions and 2 deletions.
  1. +9 −2 nmigen/back/rtlil.py
11 changes: 9 additions & 2 deletions nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
@@ -572,8 +572,15 @@ def on_Operator(self, value):
raise TypeError # :nocov:

def match_shape(self, value, new_bits, new_sign):
assert value.shape() == (new_bits, new_sign)
return self(value)
value_bits, value_sign = value.shape()
if new_bits == value_bits:
return self(value)
elif new_bits < value_bits:
return self(ast.Slice(value, 0, new_bits))
else: # new_bits > value_bits
# It is legal to assign to constants on LHS in RTLIL; such assignments are ignored.
dummy_bits = new_bits - value_bits
return "{{ {}'{} {} }}".format(dummy_bits, "x" * dummy_bits, self(value))

def on_Signal(self, value):
if value not in self.s.driven: