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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 999a2f612a56
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Aug 3, 2019

  1. vendor.lattice_ice40: add missing signal indexing.

    whitequark committed Aug 3, 2019
    Copy the full SHA
    999a2f6 View commit details
Showing with 3 additions and 3 deletions.
  1. +3 −3 nmigen/vendor/lattice_ice40.py
6 changes: 3 additions & 3 deletions nmigen/vendor/lattice_ice40.py
Original file line number Diff line number Diff line change
@@ -278,16 +278,16 @@ def get_oxor(a, invert):
elif pin.xdr == 2:
# Re-register both inputs before they enter fabric. This increases hold time
# to an entire cycle, and adds one cycle of latency.
io_args.append(("o", "D_IN_0", i0_ff))
io_args.append(("o", "D_IN_1", i1_ff))
io_args.append(("o", "D_IN_0", i0_ff[bit]))
io_args.append(("o", "D_IN_1", i1_ff[bit]))
if "o" in pin.dir:
if pin.xdr < 2:
io_args.append(("i", "D_OUT_0", pin_o[bit]))
elif pin.xdr == 2:
# Re-register negedge output after it leaves fabric. This increases setup time
# to an entire cycle, and doesn't add latency.
io_args.append(("i", "D_OUT_0", pin_o0[bit]))
io_args.append(("i", "D_OUT_1", o1_ff))
io_args.append(("i", "D_OUT_1", o1_ff[bit]))

if pin.dir in ("oe", "io"):
io_args.append(("i", "OUTPUT_ENABLE", pin.oe))