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base repository: m-labs/nmigen-boards
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head repository: m-labs/nmigen-boards
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compare: d5bea94b228b
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  • 2 commits
  • 11 files changed
  • 1 contributor

Commits on Aug 3, 2019

  1. Copy the full SHA
    bc2d42e View commit details
  2. Update all boards to use default_clk.

    whitequark committed Aug 3, 2019
    Copy the full SHA
    d5bea94 View commit details
11 changes: 4 additions & 7 deletions nmigen_boards/_blinky.py
Original file line number Diff line number Diff line change
@@ -5,14 +5,10 @@


class Blinky(Elaboratable):
def __init__(self, clk_name):
self.clk_name = clk_name

def elaborate(self, platform):
m = Module()

clk = platform.request(self.clk_name)
clk_freq = platform.get_clock_constraint(clk)
clk = platform.request(platform.default_clk)
m.domains.sync = ClockDomain()
m.d.comb += ClockSignal().eq(clk.i)

@@ -24,6 +20,7 @@ def elaborate(self, platform):
break
leds = Cat(led.o for led in leds)

clk_freq = platform.default_clk_frequency
ctr = Signal(max=int(clk_freq//2), reset=int(clk_freq//2) - 1)
with m.If(ctr == 0):
m.d.sync += ctr.eq(ctr.reset)
@@ -34,5 +31,5 @@ def elaborate(self, platform):
return m


def build_and_program(platform_cls, clk_name, **kwargs):
platform_cls().build(Blinky(clk_name), do_program=True, **kwargs)
def build_and_program(platform_cls, **kwargs):
platform_cls().build(Blinky(), do_program=True, **kwargs)
17 changes: 8 additions & 9 deletions nmigen_boards/blackice.py
Original file line number Diff line number Diff line change
@@ -10,9 +10,10 @@


class BlackIcePlatform(LatticeICE40Platform):
device = "iCE40HX4K"
package = "TQ144"
resources = [
device = "iCE40HX4K"
package = "TQ144"
default_clk = "clk100"
resources = [
Resource("clk100", 0, Pins("129", dir="i"),
Clock(100e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")
),
@@ -55,8 +56,7 @@ class BlackIcePlatform(LatticeICE40Platform):
Attrs(IO_STANDARD="SB_LVCMOS33"),
),
]

connectors = [
connectors = [
Connector("pmod", 0, " 94 91 88 85 - - 95 93 90 87 - -"), # PMOD1/2
Connector("pmod", 1, "105 102 99 97 - - 104 101 98 96 - -"), # PMOD3/4
Connector("pmod", 2, "143 114 112 107 - - 144 113 110 106 - -"), # PMOD5/6
@@ -69,10 +69,9 @@ class BlackIcePlatform(LatticeICE40Platform):

def toolchain_program(self, products, name):
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.run(["cp", bitstream_filename, "/dev/ttyACM0"], check=True)
subprocess.check_call(["cp", bitstream_filename, "/dev/ttyACM0"])


if __name__ == "__main__":
from ._blinky import Blinky
p = BlackIcePlatform()
p.build(Blinky("clk100"), do_program=True)
from ._blinky import build_and_program
build_and_program(BlackIcePlatform)
17 changes: 8 additions & 9 deletions nmigen_boards/blackice_ii.py
Original file line number Diff line number Diff line change
@@ -10,9 +10,10 @@


class BlackIceIIPlatform(LatticeICE40Platform):
device = "iCE40HX4K"
package = "TQ144"
resources = [
device = "iCE40HX4K"
package = "TQ144"
default_clk = "clk100"
resources = [
Resource("clk100", 0, Pins("129", dir="i"),
Clock(100e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")
),
@@ -57,8 +58,7 @@ class BlackIceIIPlatform(LatticeICE40Platform):
Attrs(IO_STANDARD="SB_LVCMOS33"),
),
]

connectors = [
connectors = [
Connector("pmod", 0, " 94 91 88 85 - - 95 93 90 87 - -"), # PMOD1/2
Connector("pmod", 1, "105 102 99 97 - - 104 101 98 96 - -"), # PMOD3/4
Connector("pmod", 2, "143 114 112 107 - - 144 113 110 106 - -"), # PMOD5/6
@@ -71,10 +71,9 @@ class BlackIceIIPlatform(LatticeICE40Platform):

def toolchain_program(self, products, name):
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.run(["cp", bitstream_filename, "/dev/ttyACM0"], check=True)
subprocess.check_call(["cp", bitstream_filename, "/dev/ttyACM0"])


if __name__ == "__main__":
from ._blinky import Blinky
p = BlackIceIIPlatform()
p.build(Blinky("clk100"), do_program=True)
from ._blinky import build_and_program
build_and_program(BlackIceIIPlatform)
13 changes: 7 additions & 6 deletions nmigen_boards/ice40_hx1k_blink_evn.py
Original file line number Diff line number Diff line change
@@ -10,9 +10,10 @@


class ICE40HX1KBlinkEVNPlatform(LatticeICE40Platform):
device = "iCE40HX1K"
package = "VQ100"
resources = [
device = "iCE40HX1K"
package = "VQ100"
default_clk = "clk3p3"
resources = [
Resource("clk3p3", 0, Pins("13", dir="i"), Clock(3.3e6),
Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")),

@@ -31,7 +32,7 @@ class ICE40HX1KBlinkEVNPlatform(LatticeICE40Platform):
attrs=Attrs(IO_STANDARD="SB_LVCMOS33")
),
]
connectors = [
connectors = [
Connector("pmod", 1, "10 9 8 7 - - 4 3 2 1 - -"), # J1
Connector("pmod", 5, "40 42 62 64 - - 37 41 63 45 - -"), # J5
Connector("pmod", 6, "25 24 21 20 - - 26 27 28 33 - -"), # J6
@@ -42,9 +43,9 @@ class ICE40HX1KBlinkEVNPlatform(LatticeICE40Platform):
def toolchain_program(self, products, name):
iceburn = os.environ.get("ICEBURN", "iCEburn")
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.run([iceburn, "-evw", bitstream_filename], check=True)
subprocess.check_call([iceburn, "-evw", bitstream_filename])


if __name__ == "__main__":
from ._blinky import build_and_program
build_and_program(ICE40HX1KBlinkEVNPlatform, "clk3p3")
build_and_program(ICE40HX1KBlinkEVNPlatform)
13 changes: 7 additions & 6 deletions nmigen_boards/ice40_hx8k_b_evn.py
Original file line number Diff line number Diff line change
@@ -10,9 +10,10 @@


class ICE40HX8KBEVNPlatform(LatticeICE40Platform):
device = "iCE40HX8K"
package = "CT256"
resources = [
device = "iCE40HX8K"
package = "CT256"
default_clk = "clk12"
resources = [
Resource("clk12", 0, Pins("J3", dir="i"),
Clock(12e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")),

@@ -35,7 +36,7 @@ class ICE40HX8KBEVNPlatform(LatticeICE40Platform):
attrs=Attrs(IO_STANDARD="SB_LVCMOS33")
),
]
connectors = [
connectors = [
Connector("j", 1, # J1
"A16 - A15 B15 B13 B14 - - B12 B11"
"A11 B10 A10 C9 - - A9 B9 B8 A7"
@@ -62,9 +63,9 @@ def toolchain_program(self, products, name):
iceprog = os.environ.get("ICEPROG", "iceprog")
with products.extract("{}.bin".format(name)) as bitstream_filename:
# TODO: this should be factored out and made customizable
subprocess.run([iceprog, "-S", bitstream_filename], check=True)
subprocess.check_call([iceprog, "-S", bitstream_filename])


if __name__ == "__main__":
from ._blinky import build_and_program
build_and_program(ICE40HX8KBEVNPlatform, "clk12")
build_and_program(ICE40HX8KBEVNPlatform)
11 changes: 6 additions & 5 deletions nmigen_boards/icebreaker.py
Original file line number Diff line number Diff line change
@@ -10,9 +10,10 @@


class ICEBreakerPlatform(LatticeICE40Platform):
device = "iCE40UP5K"
package = "SG48"
resources = [
device = "iCE40UP5K"
package = "SG48"
default_clk = "clk12"
resources = [
Resource("clk12", 0, Pins("35", dir="i"),
Clock(12e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")),

@@ -78,11 +79,11 @@ class ICEBreakerPlatform(LatticeICE40Platform):
def toolchain_program(self, products, name):
iceprog = os.environ.get("ICEPROG", "iceprog")
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.run([iceprog, bitstream_filename], check=True)
subprocess.check_call([iceprog, bitstream_filename])


if __name__ == "__main__":
from ._blinky import Blinky
p = ICEBreakerPlatform()
p.add_resources(p.break_off_pmod)
p.build(Blinky("clk12"), do_program=True)
p.build(Blinky(), do_program=True)
13 changes: 7 additions & 6 deletions nmigen_boards/icestick.py
Original file line number Diff line number Diff line change
@@ -11,9 +11,10 @@


class ICEStickPlatform(LatticeICE40Platform):
device = "iCE40HX1K"
package = "TQ144"
resources = [
device = "iCE40HX1K"
package = "TQ144"
default_clk = "clk12"
resources = [
Resource("clk12", 0, Pins("21", dir="i"),
Clock(12e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")),

@@ -38,7 +39,7 @@ class ICEStickPlatform(LatticeICE40Platform):
attrs=Attrs(IO_STANDARD="SB_LVCMOS33")
),
]
connectors = [
connectors = [
Connector("pmod", 0, "78 79 80 81 - - 87 88 90 91 - -"), # J2

Connector("j", 1, "- - 112 113 114 115 116 117 118 119"), # J1
@@ -48,9 +49,9 @@ class ICEStickPlatform(LatticeICE40Platform):
def toolchain_program(self, products, name):
iceprog = os.environ.get("ICEPROG", "iceprog")
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.run([iceprog, bitstream_filename], check=True)
subprocess.check_call([iceprog, bitstream_filename])


if __name__ == "__main__":
from ._blinky import build_and_program
build_and_program(ICEStickPlatform, "clk12")
build_and_program(ICEStickPlatform)
19 changes: 11 additions & 8 deletions nmigen_boards/kc705.py
Original file line number Diff line number Diff line change
@@ -10,10 +10,11 @@


class KC705Platform(Xilinx7SeriesPlatform):
device = "xc7k325t"
package = "ffg900"
speed = "2"
resources = [
device = "xc7k325t"
package = "ffg900"
speed = "2"
default_clk = "clk156"
resources = [
Resource("clk156", 0, DiffPairs("K28", "K29", dir="i"),
Clock(156e6), Attrs(IOSTANDARD="LVDS_25")),

@@ -31,15 +32,17 @@ class KC705Platform(Xilinx7SeriesPlatform):
attrs=Attrs(IOSTANDARD="LVCMOS33")
),
]
connectors = []
connectors = []

def toolchain_program(self, products, name):
openocd = os.environ.get("OPENOCD", "openocd")
with products.extract("{}.bit".format(name)) as bitstream_filename:
subprocess.run([openocd, "-c",
"source [find board/kc705.cfg]; init; pld load 0 {}; exit".format(bitstream_filename)], check=True)
subprocess.check_call([openocd,
"-c", "source [find board/kc705.cfg]; init; pld load 0 {}; exit"
.format(bitstream_filename)
])


if __name__ == "__main__":
from ._blinky import build_and_program
build_and_program(KC705Platform, "clk156")
build_and_program(KC705Platform)
13 changes: 7 additions & 6 deletions nmigen_boards/tinyfpga_bx.py
Original file line number Diff line number Diff line change
@@ -10,9 +10,10 @@


class TinyFPGABXPlatform(LatticeICE40Platform):
device = "iCE40LP8K"
package = "CM81"
resources = [
device = "iCE40LP8K"
package = "CM81"
default_clk = "clk16"
resources = [
Resource("clk16", 0, Pins("B2", dir="i"),
Clock(16e6), Attrs(IO_STANDARD="SB_LVCMOS33")),

@@ -29,7 +30,7 @@ class TinyFPGABXPlatform(LatticeICE40Platform):
cs="F7", clk="G7", mosi="G6", miso="H7", wp="H4", hold="J8",
attrs=Attrs(IO_STANDARD="SB_LVCMOS33")),
]
connectors = [
connectors = [
Connector("gpio", 0,
# Left side of the board
# 1 2 3 4 5 6 7 8 9 10 11 12 13
@@ -45,9 +46,9 @@ class TinyFPGABXPlatform(LatticeICE40Platform):
def toolchain_program(self, products, name):
tinyprog = os.environ.get("TINYPROG", "tinyprog")
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.run([tinyprog, "-p", bitstream_filename], check=True)
subprocess.check_call([tinyprog, "-p", bitstream_filename])


if __name__ == "__main__":
from ._blinky import build_and_program
build_and_program(TinyFPGABXPlatform, "clk16")
build_and_program(TinyFPGABXPlatform)
15 changes: 8 additions & 7 deletions nmigen_boards/versa_ecp5.py
Original file line number Diff line number Diff line change
@@ -10,10 +10,11 @@


class VersaECP5Platform(LatticeECP5Platform):
device = "LFE5UM-45F"
package = "BG381"
speed = "8"
resources = [
device = "LFE5UM-45F"
package = "BG381"
speed = "8"
default_clk = "clk100"
resources = [
Resource("rst", 0, PinsN("T1", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
Resource("clk100", 0, DiffPairs("P3", "P4", dir="i"),
Clock(100e6), Attrs(IO_TYPE="LVDS")),
@@ -171,12 +172,12 @@ def toolchain_program(self, products, name):
openocd = os.environ.get("OPENOCD", "openocd")
with products.extract("{}-openocd.cfg".format(name), "{}.svf".format(name)) \
as (config_filename, vector_filename):
subprocess.run([openocd,
subprocess.check_call([openocd,
"-f", config_filename,
"-c", "transport select jtag; init; svf -quiet {}; exit".format(vector_filename)
], check=True)
])


if __name__ == "__main__":
from ._blinky import build_and_program
build_and_program(VersaECP5Platform, "clk100")
build_and_program(VersaECP5Platform)
4 changes: 2 additions & 2 deletions nmigen_boards/versa_ecp5_5g.py
Original file line number Diff line number Diff line change
@@ -5,10 +5,10 @@


class VersaECP55GPlatform(VersaECP5Platform):
device = "LFE5UM5G-45F"
device = "LFE5UM5G-45F"
# Everything else is identical between 3G and 5G Versa boards.


if __name__ == "__main__":
from ._blinky import build_and_program
build_and_program(VersaECP55GPlatform, "clk100")
build_and_program(VersaECP55GPlatform)