Add Arty A7 platform. #4
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nmigen_boards/arty_a7.py
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| Resource("i2c", 0, | ||
| Subsignal("scl", Pins("L18", dir="o")), |
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This should be dir="io", in case of a multimaster design.
| Subsignal("rx_er", Pins("C17", dir="i")), | ||
| Subsignal("rx_data", Pins("D18 E17 E18 G17", dir="i")), | ||
| Subsignal("tx_en", Pins("H15", dir="o")), | ||
| Subsignal("tx_data", Pins("H14 J14 J13 H17", dir="o")), |
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I'm a bit confused--is this RGMII? Doesn't it have dv and er combined into one signal?
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According to the manual, the PHY has a MII interface.
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Ah sorry, I forgot that MII has half the pins of GMII.
nmigen_boards/arty_a7.py
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| Subsignal("tx", Pins("H16", dir="i")), | ||
| Subsignal("rx", Pins("F15", dir="i")), | ||
| Attrs(IOSTANDARD="LVCMOS33") | ||
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I think these clocks should be a part of the eth_mii resource. (That's what I've done for Versa ECP5).
nmigen_boards/arty_a7.py
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| Subsignal("rx", Pins("F15", dir="i")), | ||
| Attrs(IOSTANDARD="LVCMOS33") | ||
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| Resource("eth", 0, |
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This should be called eth_mii.
nmigen_boards/arty_a7.py
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| Attrs(SLEW="FAST"), | ||
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| Resource("eth_ref_clk", 0, Pins("G18", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), |
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Does this clock have a fixed frequency? Or does the reference clock vary too in MII?
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Yes, its frequency must be 25MHz for MII, and 50 MHz for RMII.
nmigen_boards/arty_a7.py
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| attrs=Attrs(IOSTANDARD="LVCMOS33") | ||
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| Resource("ddram", 0, |
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I think this should be called ddr2, ddr3, etc depending on actual version.
nmigen_boards/arty_a7.py
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| Resource("cpu_reset", 0, Pins("C2", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), | ||
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| Resource("spi", 0, |
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Would you be willing to add SPIResource like SPIFlashResources?
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Sure, I will do it in a later commit.
nmigen_boards/arty_a7.py
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| Subsignal("tx_en", Pins("H15", dir="o")), | ||
| Subsignal("tx_data", Pins("H14 J14 J13 H17", dir="o")), | ||
| Subsignal("col", Pins("D17", dir="i")), | ||
| Subsignal("crs", Pins("G14", dir="i")), |
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These are receiver signals logically, so I'd say these should be called rx_col and rx_crs.
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(I was wrong: in MII, COL and CRS are asynchronous.)
nmigen_boards/arty_a7.py
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| Subsignal("tx_en", Pins("H15", dir="o")), | ||
| Subsignal("tx_data", Pins("H14 J14", dir="o")), | ||
| Subsignal("rx_crs_dv", Pins("G14", dir="i")), | ||
| Subsignal("rx_dv", Pins("G16", dir="i"), Attrs(PULLUP="TRUE")), |
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OK, I believe there is only one remaining review item. Could you explain what is rx_dv here? AFAIK, in RMII there is only rx_crs_dv.
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The PHY (TI DP83848J) can operate in RMII mode by strapping rx_dv high during reset.
rx_dv can also be used in RMII mode as a simpler way to access DV, without having to extract it from rx_crs_dv.
This is according to the datasheet, I actually haven't tested RMII on the Arty.
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Thanks! |
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