-
Notifications
You must be signed in to change notification settings - Fork 13
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Add Arty A7 platform. #4
Conversation
nmigen_boards/arty_a7.py
Outdated
), | ||
|
||
Resource("i2c", 0, | ||
Subsignal("scl", Pins("L18", dir="o")), |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
This should be dir="io"
, in case of a multimaster design.
Subsignal("rx_er", Pins("C17", dir="i")), | ||
Subsignal("rx_data", Pins("D18 E17 E18 G17", dir="i")), | ||
Subsignal("tx_en", Pins("H15", dir="o")), | ||
Subsignal("tx_data", Pins("H14 J14 J13 H17", dir="o")), |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
I'm a bit confused--is this RGMII? Doesn't it have dv
and er
combined into one signal?
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
According to the manual, the PHY has a MII interface.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Ah sorry, I forgot that MII has half the pins of GMII.
nmigen_boards/arty_a7.py
Outdated
Subsignal("tx", Pins("H16", dir="i")), | ||
Subsignal("rx", Pins("F15", dir="i")), | ||
Attrs(IOSTANDARD="LVCMOS33") | ||
), |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
I think these clocks should be a part of the eth_mii
resource. (That's what I've done for Versa ECP5).
nmigen_boards/arty_a7.py
Outdated
Subsignal("rx", Pins("F15", dir="i")), | ||
Attrs(IOSTANDARD="LVCMOS33") | ||
), | ||
Resource("eth", 0, |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
This should be called eth_mii
.
nmigen_boards/arty_a7.py
Outdated
Attrs(SLEW="FAST"), | ||
), | ||
|
||
Resource("eth_ref_clk", 0, Pins("G18", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Does this clock have a fixed frequency? Or does the reference clock vary too in MII?
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Yes, its frequency must be 25MHz for MII, and 50 MHz for RMII.
nmigen_boards/arty_a7.py
Outdated
attrs=Attrs(IOSTANDARD="LVCMOS33") | ||
), | ||
|
||
Resource("ddram", 0, |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
I think this should be called ddr2
, ddr3
, etc depending on actual version.
nmigen_boards/arty_a7.py
Outdated
|
||
Resource("cpu_reset", 0, Pins("C2", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), | ||
|
||
Resource("spi", 0, |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Would you be willing to add SPIResource
like SPIFlashResources
?
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Sure, I will do it in a later commit.
nmigen_boards/arty_a7.py
Outdated
Subsignal("tx_en", Pins("H15", dir="o")), | ||
Subsignal("tx_data", Pins("H14 J14 J13 H17", dir="o")), | ||
Subsignal("col", Pins("D17", dir="i")), | ||
Subsignal("crs", Pins("G14", dir="i")), |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
These are receiver signals logically, so I'd say these should be called rx_col
and rx_crs
.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
(I was wrong: in MII, COL and CRS are asynchronous.)
nmigen_boards/arty_a7.py
Outdated
Subsignal("tx_en", Pins("H15", dir="o")), | ||
Subsignal("tx_data", Pins("H14 J14", dir="o")), | ||
Subsignal("rx_crs_dv", Pins("G14", dir="i")), | ||
Subsignal("rx_dv", Pins("G16", dir="i"), Attrs(PULLUP="TRUE")), |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
OK, I believe there is only one remaining review item. Could you explain what is rx_dv
here? AFAIK, in RMII there is only rx_crs_dv
.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
The PHY (TI DP83848J) can operate in RMII mode by strapping rx_dv
high during reset.
rx_dv
can also be used in RMII mode as a simpler way to access DV, without having to extract it from rx_crs_dv
.
This is according to the datasheet, I actually haven't tested RMII on the Arty.
Thanks! |
No description provided.