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base repository: m-labs/nmigen
base: 27063a3bd33e
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head repository: m-labs/nmigen
compare: 434b686d5e6a
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  • 2 commits
  • 3 files changed
  • 1 contributor

Commits on Aug 4, 2019

  1. vendor.xilinx_spartan_3_6: reconsider bitgen defaults. 

    Previously changed in 27063a3.

I haven't realized the .bin file is the same as the .bit file without
a small header. That means generating it is free and it's just easier
to let programming tools to be able to always rely on its existence.
    whitequark committed Aug 4, 2019
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    3d7214c View commit details
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  2. vendor.xilinx_{spartan_3_6,7series}: reconsider default reset logic. 

    On Xilinx devices, flip-flops are reset to their initial state with
an internal global reset network, but this network is deasserted
asynchronously to user clocks. Use BUFGCE and STARTUP to hold default
clock low until after GWE is deasserted.
    whitequark committed Aug 4, 2019
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    434b686 View commit details
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