There were three issues:
  * nMigen SyncFIFOBuffered no longer provides access to the inner
    FIFO. Therefore, level of the outer FIFO is used instead.
  * nMigen simulator no longer allows setting Signals that are not
    actually used anywhere in simulation.
  * In nMigen, FIFOInterface.read() is 1-cycle, not 2-cycle.
    This requires adjustment of our read loop (which would ideally
    be rewritten.)

nMigen provides a native replacement for what Pads was trying to do,
so this module is essentially deprecated, and no particular care has
been taken to keep it in good shape.

This doesn't include adjustments for gateware.platform. Fortunately,
only a few applets use PLL, so this can be done later.

nMigen now provides XDR in the platform layer, so it is no longer
necessary to instantiate SB_IO.

nMigen build plans contain all files, including the constraint files,
so it is no longer necessary to track IO placement in attributes.