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New platform creates #75

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zignig opened this issue Jun 2, 2019 · 1 comment
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New platform creates #75

zignig opened this issue Jun 2, 2019 · 1 comment
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@zignig
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zignig commented Jun 2, 2019

When generating the platform, it creates signals with double underscores and ignores the resource

zignig@noid:/opt/FPGA/nmigen/examples$ python blinky.py
Warning: net 'clk3p3_0_io' does not exist in design, ignoring clock constraint

in build/top.il

  attribute \src "/usr/local/lib/python3.6/dist-packages/nmigen/build/res.py:137"
  wire width 1 input 0 \clk3p3_0_io

and then

  wire width 1 \clk3p3_0__i
  attribute \src "/usr/local/lib/python3.6/dist-packages/nmigen/hdl/rec.py:98"
  wire width 1 $next\clk3p3_0__i
  process $group_0
    assign $next\clk 1'0
    assign $next\clk \clk3p3_0__i
    sync init
    sync always
      update \clk $next\clk
  end
@whitequark
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Duplicate of #71. Update nextpnr.

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@whitequark @zignig