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base repository: m-labs/nmigen
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compare: 2ca0834d4113
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  • 3 commits
  • 3 files changed
  • 1 contributor

Commits on Jun 3, 2019

  1. vendor.ice40_hx1k_blink_evn: add (some) connectors.

    I have no idea how to lay out the Arduino-like connectors best,
    so they're just missing.
    whitequark committed Jun 3, 2019
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    f351e2b View commit details
  2. vendor.icestick: add connectors.

    whitequark committed Jun 3, 2019
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    7c5461d View commit details
  3. vendor.tinyfpga_bx: add connectors.

    whitequark committed Jun 3, 2019
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    2ca0834 View commit details
Showing with 54 additions and 20 deletions.
  1. +11 −4 nmigen/vendor/ice40_hx1k_blink_evn.py
  2. +13 −7 nmigen/vendor/icestick.py
  3. +30 −9 nmigen/vendor/tinyfpga_bx.py
15 changes: 11 additions & 4 deletions nmigen/vendor/ice40_hx1k_blink_evn.py
Original file line number Diff line number Diff line change
@@ -6,12 +6,12 @@


class ICE40HX1KBlinkEVNPlatform(IceBurnProgrammerMixin, LatticeICE40Platform):
device = "hx1k"
package = "vq100"
clocks = [
device = "hx1k"
package = "vq100"
clocks = [
("clk3p3", 3.3e6),
]
resources = [
resources = [
Resource("clk3p3", 0, Pins("13", dir="i"),
extras={"GLOBAL": "1", "IO_STANDARD": "SB_LVCMOS33"}),

@@ -25,3 +25,10 @@ class ICE40HX1KBlinkEVNPlatform(IceBurnProgrammerMixin, LatticeICE40Platform):
Resource("user_btn", 2, Pins("54"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_btn", 3, Pins("52"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
]
connectors = [
Connector("pmod", 1, "10 9 8 7 - - 4 3 2 1 - -"), # J1
Connector("pmod", 5, "40 42 62 64 - - 37 41 63 45 - -"), # J5
Connector("pmod", 6, "25 24 21 20 - - 26 27 28 33 - -"), # J6
Connector("pmod", 11, "49 45 46 48 - -"), # J11
Connector("pmod", 12, "59 56 53 51 - -"), # J12
]
20 changes: 13 additions & 7 deletions nmigen/vendor/icestick.py
Original file line number Diff line number Diff line change
@@ -6,12 +6,12 @@


class ICEStickPlatform(IceStormProgrammerMixin, LatticeICE40Platform):
device = "hx1k"
package = "tq144"
clocks = [
device = "hx1k"
package = "tq144"
clocks = [
("clk12", 12e6),
]
resources = [
resources = [
Resource("clk12", 0, Pins("21", dir="i"),
extras={"GLOBAL": "1", "IO_STANDARD": "SB_LVCMOS33"}),

@@ -42,9 +42,15 @@ class ICEStickPlatform(IceStormProgrammerMixin, LatticeICE40Platform):
Resource("spiflash", 0,
Subsignal("cs_n", Pins("71", dir="o")),
Subsignal("clk", Pins("70", dir="o")),
Subsignal("mosi", Pins("67", dir="io")),
Subsignal("miso", Pins("68", dir="io")),
Subsignal("mosi", Pins("67", dir="o")),
Subsignal("miso", Pins("68", dir="i")),
extras={"IO_STANDARD": "SB_LVCMOS33"}
),
]
prog_mode = "flash"
connectors = [
Connector("pmod", 0, "78 79 80 81 - - 87 88 90 91 - -"), # J2

Connector("j", 1, "- - 112 113 114 115 116 117 118 119"), # J1
Connector("j", 3, "- - 62 61 60 56 48 47 45 44"), # J3
]
prog_mode = "flash"
39 changes: 30 additions & 9 deletions nmigen/vendor/tinyfpga_bx.py
Original file line number Diff line number Diff line change
@@ -6,29 +6,50 @@


class TinyFPGABXPlatform(TinyProgrammerMixin, LatticeICE40Platform):
device = "lp8k"
package = "cm81"
clocks = [
device = "lp8k"
package = "cm81"
clocks = [
("clk16", 16e6),
]
resources = [
resources = [
Resource("clk16", 0, Pins("B2", dir="i"),
extras={"GLOBAL": 1, "IO_STANDARD": "SB_LVCMOS33"}),

Resource("user_led", 0, Pins("B3", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),

Resource("usb", 0,
Subsignal("d_p", Pins("B4", dir="io")),
Subsignal("d_n", Pins("A4", dir="io")),
Subsignal("pull_up", Pins("A3", dir="o")),
Subsignal("d_p", Pins("B4", dir="io")),
Subsignal("d_n", Pins("A4", dir="io")),
Subsignal("pullup", Pins("A3", dir="o")),
extras={"IO_STANDARD": "SB_LVCMOS33"}
),

Resource("spiflash", 0,
Subsignal("cs_n", Pins("F7", dir="o")),
Subsignal("clk", Pins("G7", dir="o")),
Subsignal("mosi", Pins("G6", dir="io")),
Subsignal("miso", Pins("H7", dir="io")),
Subsignal("mosi", Pins("G6", dir="o")),
Subsignal("miso", Pins("H7", dir="i")),
Subsignal("wp", Pins("H4", dir="o")),
Subsignal("hold", Pins("J8", dir="o")),
extras={"IO_STANDARD": "SB_LVCMOS33"}
),

Resource("spiflash4x", 0,
Subsignal("cs_n", Pins("F7", dir="o")),
Subsignal("clk", Pins("G7", dir="o")),
Subsignal("dq", Pins("G6 H7 H4 J8", dir="io")),
extras={"IO_STANDARD": "SB_LVCMOS33"}
),
]
connectors = [
Connector("gpio", 0,
# Left side of the board
# 1 2 3 4 5 6 7 8 9 10 11 12 13
" A2 A1 B1 C2 C1 D2 D1 E2 E1 G2 H1 J1 H2"
# Right side of the board
# 14 15 16 17 18 19 20 21 22 23 24
" H9 D9 D8 B8 A9 B8 A8 B7 A7 B6 A6"
# Bottom of the board
# 25 26 27 28 29 30 31
"G1 J3 J4 G9 J9 E8 J2"),
]