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base repository: m-labs/nmigen
base: f417725b10de
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head repository: m-labs/nmigen
compare: 9ba2efd86b52
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  • 4 commits
  • 6 files changed
  • 1 contributor

Commits on Jun 3, 2019

  1. vendor.fpga.lattice_ice40: enable SystemVerilog when reading .sv files.

    whitequark committed Jun 3, 2019
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  2. lib.io: allow Pin(xdr=0), representing a combinatorial I/O buffer.

    whitequark committed Jun 3, 2019
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  3. build.res: allow requesting raw ports, with dir="-". 

    This provides an escape hatch for the case where the nMigen platform
code is not flexible enough, and a IO buffer primitive needs to be
instantiated directly.
    whitequark committed Jun 3, 2019
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  4. build.{res,plat}: use xdr=0 as default, not xdr=1. 

    The previous behavior was semantically incorrect.
    whitequark committed Jun 3, 2019
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