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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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  • 3 commits
  • 6 files changed
  • 1 contributor

Commits on Jun 3, 2019

  1. hdl.ir: accept LHS signals like slices as Instance io ports. 

    This is unlikely to work with anything except Slice and Cat, but
there's no especially good place to enforce it. (Maybe in Instance?)
    whitequark committed Jun 3, 2019
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  2. vendor.fpga.lattice_ice40: instantiate SB_IO and apply extras. 

    The PULLUP and PULLUP_RESISTOR extras are representable in the PCF
file. The IO_STANDARD extra, however, can only be an SB_IO parameter.
    whitequark committed Jun 3, 2019
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  3. build.res: if not specified, request resource #0. 

    This markedly differs from oMigen system, which would request
consecutive resources. The difference is deliberate; most resources
are singular, so it does not matter for them, and for resources where
it does matter, which pins are requested should not depend on order
of execution of `platform.request`.
    whitequark committed Jun 3, 2019
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