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base repository: GlasgowEmbedded/glasgow
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head repository: GlasgowEmbedded/glasgow
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compare: ffdcf8bf2cc9
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  • 3 commits
  • 5 files changed
  • 1 contributor

Commits on Jul 25, 2019

  1. applet.{display.pdi,program.avr}: disable autoflush.

    This improves performance, and also there appears to be an autoflush
    related race condition with the crossbar currently.
    whitequark committed Jul 25, 2019
    Copy the full SHA
    5679fa4 View commit details
  2. applet: fix typos.

    whitequark committed Jul 25, 2019
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    c51538b View commit details
  3. Copy the full SHA
    ffdcf8b View commit details
4 changes: 2 additions & 2 deletions software/glasgow/applet/__init__.py
Original file line number Diff line number Diff line change
@@ -42,7 +42,7 @@ def derive_clock(self, *args, clock_name=None, **kwargs):
raise GlasgowAppletError("clock {}: {}".format(clock_name, e))

def build(self, target):
raise NotImplemented
raise NotImplementedError

@classmethod
def add_run_arguments(cls, parser, access):
@@ -52,7 +52,7 @@ async def run_lower(self, cls, device, args):
return await super(cls, self).run(device, args)

async def run(self, device, args):
raise NotImplemented
raise NotImplementedError

@classmethod
def add_interact_arguments(cls, parser):
2 changes: 1 addition & 1 deletion software/glasgow/applet/display/pdi/__init__.py
Original file line number Diff line number Diff line change
@@ -345,7 +345,7 @@ def build(self, target, args):
subtarget = iface.add_subtarget(SPIMasterSubtarget(
pads=iface.get_pads(args, pins=self.__pins + self.__pins_g1),
out_fifo=iface.get_out_fifo(),
in_fifo=iface.get_in_fifo(),
in_fifo=iface.get_in_fifo(auto_flush=False),
period_cyc=math.ceil(target.sys_clk_freq / 5e6),
delay_cyc=math.ceil(target.sys_clk_freq / 1e6),
sck_idle=0,
2 changes: 1 addition & 1 deletion software/glasgow/applet/memory/_25x/__init__.py
Original file line number Diff line number Diff line change
@@ -34,7 +34,7 @@ def __init__(self, interface, logger):
def _log(self, message, *args):
self._logger.log(self._level, "25x: " + message, *args)

async def _command(self, cmd, arg=[], dummy=0, ret=0, hold_ss=False):
async def _command(self, cmd, arg=[], dummy=0, ret=0):
arg = bytes(arg)

self._log("cmd=%02X arg=<%s> dummy=%d ret=%d", cmd, dump_hex(arg), dummy, ret)
2 changes: 1 addition & 1 deletion software/glasgow/applet/program/avr/spi.py
Original file line number Diff line number Diff line change
@@ -246,7 +246,7 @@ def build(self, target, args):
subtarget = iface.add_subtarget(SPIMasterSubtarget(
pads=iface.get_pads(args, pins=self.__pins),
out_fifo=iface.get_out_fifo(),
in_fifo=iface.get_in_fifo(),
in_fifo=iface.get_in_fifo(auto_flush=False),
period_cyc=math.ceil(target.sys_clk_freq / (args.bit_rate * 1000)),
delay_cyc=math.ceil(target.sys_clk_freq / 1e6),
sck_idle=0,
1 change: 0 additions & 1 deletion software/glasgow/applet/program/ice40_sram/__init__.py
Original file line number Diff line number Diff line change
@@ -111,7 +111,6 @@ async def interact(self, device, args, ice40_iface):
else:
self.logger.warning("FPGA failed to configure after releasing reset")


# -------------------------------------------------------------------------------------------------

class ProgramICE40SRAMAppletTestCase(GlasgowAppletTestCase, applet=ProgramICE40SRAMApplet):