support for memories with N read-only ports + 1 write-only port? #153
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You can already do this: simply request the appropriate amount of read ports by calling |
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Hmm. One would have to check that carefully (I remember problems with ISE a long time ago), though this would be one of many issues that would disappear if we let Yosys synthesize memories for all FPGA families. |
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According to IRC conversation with @cr1901, ISE and Vivado can do that. |
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Rationale: The default config file of |
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Closing; please reopen if there are actual toolchain bugs we need to work around. |
One trick I've used several times to implement a memory with several (typically N=2...4) read ports plus one write port is to use N dual-port memories with, for each memory, one port used for reading and one port used for writing. The individual write ports are connected in parallel to form the write port into what is the equivalent of a N+1-port memory with N read-only port and 1 write-only port.
Should nMigen automatically implement this pattern when applicable, or should this be done manually by the user?
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