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base repository: GlasgowEmbedded/glasgow
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head repository: GlasgowEmbedded/glasgow
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compare: bedeca8c0ee8
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  • 5 commits
  • 21 files changed
  • 1 contributor

Commits on Aug 2, 2019

  1. support.{bits→bitstruct} 

    Also rename Bitfield to bitstruct.
    @whitequark
    whitequark committed Aug 2, 2019
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    57b7632 View commit details

  2. support.bits: new container.

    @whitequark
    whitequark committed Aug 2, 2019
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    2ba63d2 View commit details

  3. support.bitstruct: rework to use support.bits internally.

    @whitequark
    whitequark committed Aug 2, 2019
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    c008a75 View commit details

  4. support.logging: add dump_bin(), for dumping bits. 

    This method dumps bits from LSB to MSB, in logical order. This
notably does not match the literal order.
    @whitequark
    whitequark committed Aug 2, 2019
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    57984c3 View commit details

  5. Replace inappropriate uses of bitarray with support.bits. 

      * Never trip up on endian="little" again.
  * Never reverse bit literals compared to the datasheet again.
  * Rely only on Python builtins and not C extensions.

A few cases (JESD3C fuses, PDI bitmaps) actually call for a bitarray,
so those are kept as-is.
    @whitequark
    whitequark committed Aug 2, 2019
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    bedeca8 View commit details
12 changes: 6 additions & 6 deletions software/glasgow/applet/debug/arc/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -42,7 +42,7 @@ def _log(self, message, *args):
async def identify(self):
await self.lower.write_ir(IR_IDCODE)
idcode_bits = await self.lower.read_dr(32)
idcode = DR_IDCODE.from_bitarray(idcode_bits)
idcode = DR_IDCODE.from_bits(idcode_bits)
self._log("read IDCODE mfg_id=%03x arc_type=%02x arc_number=%03x",
idcode.mfg_id, idcode.part_id & 0b111111, idcode.part_id >> 6)
device = devices[idcode.mfg_id, idcode.part_id & 0b111111]
@@ -53,7 +53,7 @@ async def _wait_txn(self):
status = DR_STATUS()
while not status.RD:
status_bits = await self.lower.read_dr(4)
status = DR_STATUS.from_bitarray(status_bits)
status = DR_STATUS.from_bits(status_bits)
self._log("status %s", status.bits_repr())
if status.FL:
raise ARCDebugError("transaction failed: %s" % status.bits_repr())
@@ -71,14 +71,14 @@ async def read(self, address, space):
self._log("read %s address=%08x", space, address)
dr_address = DR_ADDRESS(Address=address)
await self.lower.write_ir(IR_ADDRESS)
await self.lower.write_dr(dr_address.to_bitarray())
await self.lower.write_dr(dr_address.to_bits())
await self.lower.write_ir(IR_TXN_COMMAND)
await self.lower.write_dr(dr_txn_command)
await self.lower.run_test_idle(1)
await self._wait_txn()
await self.lower.write_ir(IR_DATA)
dr_data_bits = await self.lower.read_dr(32)
dr_data = DR_DATA.from_bitarray(dr_data_bits)
dr_data = DR_DATA.from_bits(dr_data_bits)
self._log("read data=%08x", dr_data.Data)
return dr_data.Data

@@ -95,10 +95,10 @@ async def write(self, address, data, space):
self._log("write %s address=%08x data=%08x", space, address, data)
dr_address = DR_ADDRESS(Address=address)
await self.lower.write_ir(IR_ADDRESS)
await self.lower.write_dr(dr_address.to_bitarray())
await self.lower.write_dr(dr_address.to_bits())
await self.lower.write_ir(IR_DATA)
dr_data = DR_DATA(Data=data)
await self.lower.write_dr(dr_data.to_bitarray())
await self.lower.write_dr(dr_data.to_bits())
await self.lower.write_ir(IR_TXN_COMMAND)
await self.lower.write_dr(dr_txn_command)
await self.lower.run_test_idle(1)
29 changes: 10 additions & 19 deletions software/glasgow/applet/debug/mips/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -5,10 +5,10 @@
import struct
import logging
import asyncio
from bitarray import bitarray

from ....support.aobject import *
from ....support.endpoint import *
from ....support.bits import *
from ....support.pyrepl import *
from ....arch.mips import *
from ....protocol.gdb_remote import *
@@ -54,7 +54,7 @@ def _change_state(self, state):
async def _read_impcode(self):
await self.lower.write_ir(IR_IMPCODE)
impcode_bits = await self.lower.read_dr(32)
self._impcode = DR_IMPCODE.from_bitarray(impcode_bits)
self._impcode = DR_IMPCODE.from_bits(impcode_bits)
self._log("read IMPCODE %s", self._impcode.bits_repr())

async def _exchange_control(self, **fields):
@@ -67,11 +67,11 @@ async def _exchange_control(self, **fields):
control.PrAcc = 1
for field, value in fields.items():
setattr(control, field, value)
control_bits = control.to_bitarray()
control_bits = control.to_bits()
await self.lower.write_ir(IR_CONTROL)

control_bits = await self.lower.exchange_dr(control_bits)
new_control = DR_CONTROL.from_bitarray(control_bits)
new_control = DR_CONTROL.from_bits(control_bits)
self._log("read CONTROL %s", new_control.bits_repr(omit_zero=True))

if new_control.Rocc and control.Rocc:
@@ -96,38 +96,29 @@ async def _scan_address_length(self):
async def _read_address(self):
await self.lower.write_ir(IR_ADDRESS)
address_bits = await self.lower.read_dr(self._address_length)
address_bits.extend(address_bits[-1:] * (64 - self._address_length))
address, = struct.unpack("<q", address_bits.tobytes())
address &= self._mask
address_bits = address_bits + address_bits[-1:] * (64 - self._address_length)
address = int(address_bits) & self._mask
self._log("read ADDRESS %#0.*x", self._prec, address)
return address

async def _write_address(self, address):
# See _read_address. NB: ADDRESS is only writable in EJTAG v1.x/2.0 with DMAAcc.
self._log("write ADDRESS %#0.*x", self._prec, address)
address_bits = bitarray(endian="little")
address_bits.frombytes(struct.pack("<Q", address))
address_bits = bits(address, self._address_length)
await self.lower.write_ir(IR_ADDRESS)
await self.lower.write_dr(address_bits[:self._address_length])
await self.lower.write_dr(address_bits)

async def _read_data(self):
await self.lower.write_ir(IR_DATA)
data_bits = await self.lower.read_dr(self.bits)
if self.bits == 32:
data, = struct.unpack("<L", data_bits.tobytes())
elif self.bits == 64:
data, = struct.unpack("<Q", data_bits.tobytes())
data = int(data_bits)
self._log("read DATA %#0.*x", self._prec, data)
return data

async def _write_data(self, data):
self._log("write DATA %#0.*x", self._prec, data)
await self.lower.write_ir(IR_DATA)
data_bits = bitarray(endian="little")
if self.bits == 32:
data_bits.frombytes(struct.pack("<L", data))
elif self.bits == 64:
data_bits.frombytes(struct.pack("<Q", data))
data_bits = bits(data, self.bits)
await self.lower.write_dr(data_bits)

# DMAAcc memory read/write
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