GlasgowEmbedded · Aug 2, 2019 · Aug 2, 2019 · Aug 2, 2019
diff --git a/software/glasgow/applet/all.py b/software/glasgow/applet/all.py
@@ -18,6 +18,7 @@
 from .debug.arc import DebugARCApplet
 from .debug.mips import DebugMIPSApplet
 from .debug.arm.swd import DebugARMSWDApplet
+from .debug.msp430 import DebugMSP430JTAGApplet, DebugMSP430SBWApplet
 
 from .program.avr.spi import ProgramAVRSPIApplet
 from .program.ice40_flash import ProgramICE40FlashApplet

diff --git a/software/glasgow/applet/debug/mips/__init__.py b/software/glasgow/applet/debug/mips/__init__.py
@@ -829,7 +829,7 @@ def add_run_arguments(cls, parser, access):
             help="select TAP #INDEX for communication (default: %(default)s)")
 
     async def run(self, device, args):
-        jtag_iface = await super().run(device, args)
+        jtag_iface = await self.run_lower(DebugMIPSApplet, device, args)
         tap_iface = await jtag_iface.select_tap(args.tap_index)
         if not tap_iface:
             raise GlasgowAppletError("cannot select TAP #%d" % args.tap_index)

diff --git a/software/glasgow/applet/debug/msp430/__init__.py b/software/glasgow/applet/debug/msp430/__init__.py
@@ -0,0 +1,91 @@
+# Ref: MSP430™ Programming With the JTAG Interface
+# Accession: G00038
+
+# Note: for unknown reasons, DR values and captured IR value are bit reversed. However, IR opcodes
+# are not bit reversed. This is quite confusing.
+
+import logging
+import asyncio
+from abc import ABCMeta, abstractmethod
+
+from ....support.aobject import *
+from ....support.bits import *
+from ....arch.msp430.jtag import *
+from ...interface.jtag_probe import JTAGProbeApplet
+from ...interface.sbw_probe import SpyBiWireProbeApplet
+from ... import *
+
+
+class MSP430DebugError(GlasgowAppletError):
+    pass
+
+
+class MSP430FamilyDebugInterface(aobject, metaclass=ABCMeta):
+    async def __init__(self, interface, logger):
+        self.lower   = interface
+        self._logger = logger
+        self._level  = logging.DEBUG if self._logger.name == __name__ else logging.TRACE
+
+    def _log(self, message, *args):
+        self._logger.log(self._level, "MSP430: " + message, *args)
+
+    @abstractmethod
+    async def attach(self):
+        pass
+
+
+class MSP430DebugInterface(MSP430FamilyDebugInterface):
+    async def _set_control(self, **kwargs):
+        cntrl_sig = DR_CNTRL_SIG_124(R_W=1, TAGFUNCSAT=1, TCE1=1)
+        cntrl_sig_bits = cntrl_sig.to_bits()
+        self._log("set CNTRL_SIG %s", cntrl_sig.bits_repr(omit_zero=True))
+        await self.lower.write_ir(IR_CNTRL_SIG_16BIT)
+        await self.lower.write_dr(cntrl_sig_bits.reversed())
+
+    async def _get_control(self):
+        await self.lower.write_ir(IR_CNTRL_SIG_CAPTURE)
+        cntrl_sig_bits = await self.lower.read_dr(16)
+        cntrl_sig = DR_CNTRL_SIG_124.from_bits(cntrl_sig_bits.reversed())
+        self._log("get CNTRL_SIG %s", cntrl_sig.bits_repr(omit_zero=True))
+        return cntrl_sig
+
+    async def attach(self):
+        self._log("attach")
+        await self._set_control(R_W=1, TAGFUNCSAT=1, TCE1=1)
+        cntrl_sig = await self._get_control()
+        if not cntrl_sig.TCE:
+            raise MSP430DebugError("cannot attach to target")
+
+
+class DebugMSP430AppletMixin:
+    preview = True
+    description = "" # nothing to add for now
+
+    async def interact(self, device, args, msp430_iface):
+        await msp430_iface.attach()
+
+
+class DebugMSP430JTAGApplet(DebugMSP430AppletMixin, JTAGProbeApplet, name="debug-msp430-jtag"):
+    logger = logging.getLogger(__name__)
+    help = "debug MSP430 processors via JTAG"
+    description = """
+    Debug Texas Instruments MSP430 processors via the 4-wire JTAG interface.
+    """ + DebugMSP430AppletMixin.description
+
+    async def run(self, device, args):
+        jtag_iface = await self.run_lower(DebugMSP430JTAGApplet, device, args)
+        await jtag_iface.test_reset()
+        return await MSP430DebugInterface(jtag_iface, self.logger)
+
+
+class DebugMSP430SBWApplet(DebugMSP430AppletMixin, SpyBiWireProbeApplet, name="debug-msp430-sbw"):
+    logger = logging.getLogger(__name__)
+    help = "debug MSP430 processors via Spy-Bi-Wire"
+    description = """
+    Debug Texas Instruments MSP430 processors via the 2-wire Spy-Bi-Wire interface.
+    """ + DebugMSP430AppletMixin.description
+
+    async def run(self, device, args):
+        jtag_iface = await self.run_lower(DebugMSP430SBWApplet, device, args)
+        await jtag_iface.test_reset()
+        return await MSP430DebugInterface(jtag_iface, self.logger)
diff --git a/software/glasgow/applet/interface/sbw_probe/__init__.py b/software/glasgow/applet/interface/sbw_probe/__init__.py
@@ -174,7 +174,8 @@ async def run(self, device, args):
 
     async def interact(self, device, args, jtag_iface):
         await jtag_iface.test_reset()
-        version = int(await jtag_iface.read_ir(8))
+        version_bits = await jtag_iface.read_ir(8)
+        version = int(version_bits.reversed())
         if version == 0xff:
             self.logger.error("no target detected; connection problem?")
         else:

diff --git a/software/glasgow/support/bits.py b/software/glasgow/support/bits.py
@@ -174,6 +174,14 @@ def __rxor__(self, other):
         other = self.__class__(other)
         return self ^ other
 
+    def reversed(self):
+        value = 0
+        for bit in range(self._len_):
+            value <<= 1
+            if (self._int_ >> bit) & 1:
+                value |= 1
+        return self.__class__(value, self._len_)
+
 # -------------------------------------------------------------------------------------------------
 
 import unittest
@@ -330,3 +338,6 @@ def test_xor(self):
         self.assertBits(bits("1010") ^ bits("1100"), 4, 0b0110)
         self.assertBits(bits("1010") ^ "1100", 4, 0b0110)
         self.assertBits((0,1,0,1) ^ bits("1100"), 4, 0b0110)
+
+    def test_reversed(self):
+        self.assertBits(bits("1010").reversed(), 4, 0b0101)