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Platform default clock #169

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zignig opened this issue Aug 5, 2019 · 2 comments
Closed

Platform default clock #169

zignig opened this issue Aug 5, 2019 · 2 comments
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@zignig
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zignig commented Aug 5, 2019

Updated to the latest nmigen/nimgen-boards and the defined clock for my tinybx platform stopped working.

The following code

def elaborate(self, platform):
        clk16 = platform.request("clk16", 0)

        m = Module()
        m.domains.sync = ClockDomain()
        m.d.comb += ClockSignal().eq(clk16.i)

        m.submodules.boneless = self.b
        return m

returns a long error ending in

  File "/usr/local/lib/python3.6/dist-packages/nmigen/hdl/ir.py", line 305, in _propagate_domains_up
    subfrag._propagate_domains_up(hierarchy + (hier_name,))
  File "/usr/local/lib/python3.6/dist-packages/nmigen/hdl/ir.py", line 341, in _propagate_domains_up
    self.add_domains(subfrag.domains[domain])
  File "/usr/local/lib/python3.6/dist-packages/nmigen/hdl/ir.py", line 140, in add_domains
    assert domain.name not in self.domains
AssertionError

Tried removing the clocking all together to try to get the new default_clk to connect , same issue.

Bisected it down to 8854ca0 , not sure why it's not getting the default clock, or taking the existing one.

@whitequark whitequark added the bug label Aug 5, 2019
@whitequark whitequark added this to the 0.1 milestone Aug 5, 2019
@whitequark
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Yes, known bug. I'll fix it soon.

@Fatsie
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Fatsie commented Aug 10, 2019

I have same assertion but caused by use of hierarchical modules. Reporting as extra test case:

#!/bin/env python3
from nmigen import *

from nmigen_boards.icebreaker import ICEBreakerPlatform

class SubMod(Elaboratable):
    def __init__(self):
        self.i = Signal()
        self.o = Signal()

    def elaborate(self, platform):
        m = Module()

        m.d.sync += self.o.eq(self.i)

        return m


class Top(Elaboratable):
    def elaborate(self, platform):
        m = Module()

        sw = platform.request("user_btn")
        led = platform.request("user_led")

        m.submodules.submod = submod = SubMod()

        m.d.comb += [
            submod.i.eq(sw.i),
            led.o.eq(submod.o),
        ]

        return m

plan = ICEBreakerPlatform().build(Top(), do_build=False)

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