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base repository: m-labs/nmigen-boards
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head repository: m-labs/nmigen-boards
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Jul 3, 2019

  1. add KC705

    sbourdeauducq committed Jul 3, 2019
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    0bcb609 View commit details
Showing with 45 additions and 0 deletions.
  1. +45 −0 nmigen_boards/kc705.py
45 changes: 45 additions & 0 deletions nmigen_boards/kc705.py
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import os
import subprocess

from nmigen.build import *
from nmigen.vendor.xilinx_7series import *
from .dev import *


__all__ = ["KC705Platform"]


class KC705Platform(Xilinx7SeriesPlatform):
device = "xc7k325t"
package = "ffg900"
speed = "2"
resources = [
Resource("clk156", 0, DiffPairs("K28", "K29", dir="i"),
Clock(156e6), Attrs(IOSTANDARD="LVDS_25")),

Resource("user_led", 0, Pins("AB8", dir="o"), Attrs(IOSTANDARD="LVCMOS15")),
Resource("user_led", 1, Pins("AA8", dir="o"), Attrs(IOSTANDARD="LVCMOS15")),
Resource("user_led", 2, Pins("AC9", dir="o"), Attrs(IOSTANDARD="LVCMOS15")),
Resource("user_led", 3, Pins("AB9", dir="o"), Attrs(IOSTANDARD="LVCMOS15")),
Resource("user_led", 4, Pins("AE26", dir="o"), Attrs(IOSTANDARD="LVCMOS15")),
Resource("user_led", 5, Pins("G19", dir="o"), Attrs(IOSTANDARD="LVCMOS15")),
Resource("user_led", 6, Pins("E18", dir="o"), Attrs(IOSTANDARD="LVCMOS15")),
Resource("user_led", 7, Pins("F16", dir="o"), Attrs(IOSTANDARD="LVCMOS15")),

UARTResource(0,
rx="M19", tx="K24",
attrs=Attrs(IOSTANDARD="LVCMOS33")
),
]
connectors = []

def toolchain_program(self, products, name):
openocd = os.environ.get("OPENOCD", "openocd")
with products.extract("{}.bit".format(name)) as bitstream_filename:
subprocess.run([openocd, "-c",
"source [find board/kc705.cfg]; init; pld load 0 bitstream_filename; exit".format(bitstream_filename)], check=True)


if __name__ == "__main__":
from ._blinky import build_and_program
build_and_program(KC705Platform, "clk156")