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base repository: m-labs/nmigen
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compare: eeb6aca93d1d
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  • 3 commits
  • 2 files changed
  • 1 contributor

Commits on Jul 3, 2019

  1. compat.fhdl.structure: fix If/Elif/Else after 3244683.

    whitequark committed Jul 3, 2019
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    9eb8160 View commit details
  2. compat.fhdl.specials: fix Memory.get_port() after 94e8f47.

    This also makes sure the native ports are instantiated for correct
    clock domain.
    whitequark committed Jul 3, 2019
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    c98b8f7 View commit details
  3. compat.fhdl.specials: use "sync" as default domain, not "sys".

    In compat.fhdl.module, we already default to "sync" as the default
    clocked domain. Using "sys" in memories only would be inconsistent
    and result in more bugs.
    whitequark committed Jul 3, 2019
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    eeb6aca View commit details
Showing with 9 additions and 8 deletions.
  1. +5 −4 nmigen/compat/fhdl/specials.py
  2. +4 −4 nmigen/compat/fhdl/structure.py
9 changes: 5 additions & 4 deletions nmigen/compat/fhdl/specials.py
Original file line number Diff line number Diff line change
@@ -65,7 +65,7 @@ def elaborate(self, platform):

class _MemoryPort(CompatModule):
def __init__(self, adr, dat_r, we=None, dat_w=None, async_read=False, re=None,
we_granularity=0, mode=WRITE_FIRST, clock_domain="sys"):
we_granularity=0, mode=WRITE_FIRST, clock_domain="sync"):
self.adr = adr
self.dat_r = dat_r
self.we = we
@@ -86,7 +86,7 @@ def elaborate(self, platform):
class CompatMemory(NativeMemory):
@deprecated("instead of `get_port()`, use `read_port()` and `write_port()`")
def get_port(self, write_capable=False, async_read=False, has_re=False, we_granularity=0,
mode=WRITE_FIRST, clock_domain="sys"):
mode=WRITE_FIRST, clock_domain="sync"):
if we_granularity >= self.width:
warnings.warn("do not specify `we_granularity` greater than memory width, as it "
"is a hard error in non-compatibility mode",
@@ -98,12 +98,13 @@ def get_port(self, write_capable=False, async_read=False, has_re=False, we_granu
DeprecationWarning, stacklevel=1)
we_granularity = None
assert mode != NO_CHANGE
rdport = self.read_port(synchronous=not async_read, transparent=mode == WRITE_FIRST)
rdport = self.read_port(domain="comb" if async_read else clock_domain,
transparent=mode == WRITE_FIRST)
rdport.addr.name = "{}_addr".format(self.name)
adr = rdport.addr
dat_r = rdport.data
if write_capable:
wrport = self.write_port(granularity=we_granularity)
wrport = self.write_port(domain=clock_domain, granularity=we_granularity)
wrport.addr = rdport.addr
we = wrport.en
dat_w = wrport.data
8 changes: 4 additions & 4 deletions nmigen/compat/fhdl/structure.py
Original file line number Diff line number Diff line change
@@ -55,21 +55,21 @@ def __init__(self, cond, *stmts):
cond = Value.wrap(cond)
if len(cond) != 1:
cond = cond.bool()
super().__init__(cond, {"1": ast.Statement.wrap(stmts)})
super().__init__(cond, {("1",): ast.Statement.wrap(stmts)})

@deprecated("instead of `.Elif(cond, ...)`, use `with m.Elif(cond): ...`")
def Elif(self, cond, *stmts):
cond = Value.wrap(cond)
if len(cond) != 1:
cond = cond.bool()
self.cases = OrderedDict(("-" + k, v) for k, v in self.cases.items())
self.cases["1" + "-" * len(self.test)] = ast.Statement.wrap(stmts)
self.cases = OrderedDict((("-" + k,), v) for (k,), v in self.cases.items())
self.cases[("1" + "-" * len(self.test),)] = ast.Statement.wrap(stmts)
self.test = Cat(self.test, cond)
return self

@deprecated("instead of `.Else(...)`, use `with m.Else(): ...`")
def Else(self, *stmts):
self.cases["-" * len(self.test)] = ast.Statement.wrap(stmts)
self.cases[()] = ast.Statement.wrap(stmts)
return self