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base repository: m-labs/nmigen
base: 9a1048af50aa
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head repository: m-labs/nmigen
compare: eeb6aca93d1d
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  • 3 commits
  • 2 files changed
  • 1 contributor

Commits on Jul 3, 2019

  1. compat.fhdl.structure: fix If/Elif/Else after 3244683.

    whitequark committed Jul 3, 2019
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  2. compat.fhdl.specials: fix Memory.get_port() after 94e8f47. 

    This also makes sure the native ports are instantiated for correct
clock domain.
    whitequark committed Jul 3, 2019
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  3. compat.fhdl.specials: use "sync" as default domain, not "sys". 

    In compat.fhdl.module, we already default to "sync" as the default
clocked domain. Using "sys" in memories only would be inconsistent
and result in more bugs.
    whitequark committed Jul 3, 2019
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