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base repository: whitequark/Boneless-CPU
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head repository: whitequark/Boneless-CPU
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compare: 7092cdd4d3f6
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  • 3 commits
  • 6 files changed
  • 1 contributor

Commits on Jul 1, 2019

  1. gateware.decoder_v3: implement ImmediateDecoder.

    @whitequark
    whitequark committed Jul 1, 2019
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    f9a732f View commit details

  2. gateware.decoder_v3: implement InstructionDecoder.

    @whitequark
    whitequark committed Jul 1, 2019
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    02e7cd1 View commit details

  3. gateware.core_v3: implement BusArbiter.

    @whitequark
    whitequark committed Jul 1, 2019
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    7092cdd View commit details
Showing with 607 additions and 70 deletions.
  1. +36 −17 boneless/arch/opcode_v3.py
  2. +95 −49 boneless/gateware/core_v3.py
  3. +472 −0 boneless/gateware/decoder_v3.py
  4. BIN doc/design.ods
  5. +2 −2 doc/manual/insns/MOVI.tex
  6. +2 −2 doc/manual/insns/MOVR.tex
53 changes: 36 additions & 17 deletions boneless/arch/opcode_v3.py
View file
Original file line number Diff line number Diff line change
@@ -1,35 +1,54 @@
OPCODE4_LOGIC = 0b0000
OPTYPE2_AND = 0b00
OPTYPE2_OR = 0b01
OPTYPE2_XOR = 0b10
OPTYPE2_CMP = 0b11
OPTYPE2_AND = 0b00
OPTYPE2_OR = 0b01
OPTYPE2_XOR = 0b10
OPTYPE2_CMP = 0b11

OPCODE4_ARITH = 0b0001
OPTYPE2_ADD = 0b00
OPTYPE2_ADC = 0b01
OPTYPE2_SUB = 0b10
OPTYPE2_SBB = 0b11
OPTYPE2_ADD = 0b00
OPTYPE2_ADC = 0b01
OPTYPE2_SUB = 0b10
OPTYPE2_SBB = 0b11

OPCODE4_SHIFT = 0b0010
OPTYPE2_SLL = 0b00
OPTYPE2_ROT = 0b01
OPTYPE2_SRL = 0b10
OPTYPE2_SRA = 0b11
OPTYPE2_SLL = 0b00
OPTYPE2_ROT = 0b01
OPTYPE2_SRL = 0b10
OPTYPE2_SRA = 0b11

OPCODE4_LD_M = 0b0100
OPCODE5_LD = 0b01000
OPCODE5_LDR = 0b01001
OPCODE5_ST = 0b01010
OPCODE5_STR = 0b01011

OPCODE4_LDX_M = 0b0110
OPCODE5_LDX = 0b01100
OPCODE5_LDXA = 0b01101

OPCODE4_ST_M = 0b0101
OPCODE5_ST = 0b01010
OPCODE5_STR = 0b01011

OPCODE4_STX_M = 0b0111
OPCODE5_STX = 0b01110
OPCODE5_STXA = 0b01111

OPCODE5_MOVR = 0b10000
OPCODE5_MOVI = 0b10001

OPCODE4_MOV_M = 0b1000
OPCODE5_MOVI = 0b10000
OPCODE5_MOVR = 0b10001

OPCODE4_FLOW = 0b1010
OPCODE5_IFLOW = 0b10100
OPTYPE3_STW = 0b000
OPTYPE3_SWPW = 0b001
OPTYPE3_ADJW = 0b010
OPTYPE3_LDW = 0b011
OPTYPE3_JR = 0b100
# OPTYPE3_? = 0b101
OPTYPE3_JV = 0b110
OPTYPE3_JT = 0b111
OPCODE5_JAL = 0b10101

OPCODE4_JCC_M = 0b1011
OPCODE5_JCC0 = 0b10110
OPCODE5_JCC1 = 0b10111

144 changes: 95 additions & 49 deletions boneless/gateware/core_v3.py
View file
Original file line number Diff line number Diff line change
@@ -1,63 +1,107 @@
from nmigen import *


class Arbiter:
MUX_PTR_REG = 0b0
MUX_PTR_PTR = 0b1

MUX_REG_A = 0b00
MUX_REG_B = 0b01
MUX_REG_SD = 0b10

def __init__(self, rdport, wrport):
self.rdport = rdport
self.wrport = wrport

self.i_win = Signal(13)
from .alsru import *


class BusArbiter(Elaboratable):
MUX_ADDR_x = 0
MUX_ADDR_REG = 0b0
MUX_ADDR_PTR = 0b1

MUX_REG_x = 0
MUX_REG_PC = 0b00
MUX_REG_A = 0b01
MUX_REG_B = 0b10
MUX_REG_SD = 0b11

MUX_OP_x = 0b0_00
MUX_OP_RD = 0b1_00
MUX_OP_RDX = 0b1_10
MUX_OP_WR = 0b1_01
MUX_OP_WRX = 0b1_11

BITS_MODE = 5
CTRL_x = Cat(C(MUX_ADDR_x, 1), C(MUX_REG_x, 2), C(MUX_OP_x, 3))
CTRL_LD_PC = Cat(C(MUX_ADDR_REG, 1), C(MUX_REG_PC, 2), C(MUX_OP_RD, 3))
CTRL_LD_RA = Cat(C(MUX_ADDR_REG, 1), C(MUX_REG_A, 2), C(MUX_OP_RD, 3))
CTRL_LD_RB = Cat(C(MUX_ADDR_REG, 1), C(MUX_REG_B, 2), C(MUX_OP_RD, 3))
CTRL_LD_RSD = Cat(C(MUX_ADDR_REG, 1), C(MUX_REG_SD, 2), C(MUX_OP_RD, 3))
CTRL_ST_RSD = Cat(C(MUX_ADDR_REG, 1), C(MUX_REG_SD, 2), C(MUX_OP_WR, 3))
CTRL_LD_MEM = Cat(C(MUX_ADDR_PTR, 1), C(MUX_REG_x, 2), C(MUX_OP_RD, 3))
CTRL_ST_MEM = Cat(C(MUX_ADDR_PTR, 1), C(MUX_REG_x, 2), C(MUX_OP_WR, 3))
CTRL_LD_EXT = Cat(C(MUX_ADDR_PTR, 1), C(MUX_REG_x, 2), C(MUX_OP_RDX, 3))
CTRL_ST_EXT = Cat(C(MUX_ADDR_PTR, 1), C(MUX_REG_x, 2), C(MUX_OP_WRX, 3))

def __init__(self):
self.i_pc = Signal(16)
self.i_w = Signal(13)
self.i_ra = Signal(3)
self.i_rb = Signal(3)
self.i_rsd = Signal(3)
self.i_ptr = Signal(16)

self.i_data = Signal(16)
self.o_data = Signal(16)

self.s_addr = Signal(16)

self.ctrl = Record([
("ptr", 1),
("reg", 2),
("we", 1),
self.c_mode = Record([
("addr", 1),
("reg", 2),
("op", 2),
])

self.o_bus_addr = Signal(16)

self.i_mem_data = Signal(16)
self.o_mem_re = Signal()
self.o_mem_data = Signal(16)
self.o_mem_we = Signal()

self.i_ext_data = Signal(16)
self.o_ext_re = Signal()
self.o_ext_data = Signal(16)
self.o_ext_we = Signal()

def elaborate(self, platform):
m = Module()

m.submodules.rdport = self.rdport
m.submodules.wrport = self.wrport

with m.Switch(self.ctrl.ptr):
with m.Case(self.MUX_PTR_REG):
with m.Switch(self.ctrl.reg):
with m.Switch(self.c_mode.addr):
with m.Case(self.MUX_ADDR_REG):
with m.Switch(self.c_mode.reg):
with m.Case(self.MUX_REG_PC):
m.d.comb += self.o_bus_addr.eq(self.i_pc)
with m.Case(self.MUX_REG_A):
m.d.comb += self.s_addr.eq(Cat(self.i_ra, self.i_win))
m.d.comb += self.o_bus_addr.eq(Cat(self.i_ra, self.i_w))
with m.Case(self.MUX_REG_B):
m.d.comb += self.s_addr.eq(Cat(self.i_rb, self.i_win))
m.d.comb += self.o_bus_addr.eq(Cat(self.i_rb, self.i_w))
with m.Case(self.MUX_REG_SD):
m.d.comb += self.s_addr.eq(Cat(self.i_rsd, self.i_win))
with m.Case(self.MUX_PTR_PTR):
m.d.comb += self.s_addr.eq(self.i_ptr)

m.d.comb += [
self.rdport.addr.eq(self.s_addr),
self.wrport.addr.eq(self.s_addr),
self.o_data.eq(self.rdport.data),
self.wrport.data.eq(self.i_data),
self.rdport.en.eq(1),
self.wrport.en.eq(self.ctrl.we),
m.d.comb += self.o_bus_addr.eq(Cat(self.i_rsd, self.i_w))
with m.Case(self.MUX_ADDR_PTR):
m.d.comb += self.o_bus_addr.eq(self.i_ptr)

with m.Switch(self.c_mode.op):
with m.Case(self.MUX_OP_RD):
m.d.comb += self.o_mem_re.eq(1)
with m.Case(self.MUX_OP_RDX):
m.d.comb += self.o_ext_re.eq(1)
with m.Case(self.MUX_OP_WR):
m.d.comb += self.o_mem_we.eq(1)
with m.Case(self.MUX_OP_WRX):
m.d.comb += self.o_ext_we.eq(1)

r_mem_re = Signal()
r_ext_re = Signal()
m.d.sync += [
r_mem_re.eq(self.o_mem_re),
r_ext_re.eq(self.o_ext_re),
]

return m.lower(platform)
m.d.comb += self.o_mem_data.eq(self.i_data)
m.d.comb += self.o_ext_data.eq(self.i_data)
with m.If(r_mem_re):
m.d.comb += self.o_data.eq(self.i_mem_data)
with m.If(r_ext_re):
m.d.comb += self.o_data.eq(self.i_ext_data)

return m

# -------------------------------------------------------------------------------------------------

@@ -67,18 +111,20 @@ def elaborate(self, platform):

if __name__ == "__main__":
parser = argparse.ArgumentParser()
parser.add_argument("type", choices=["arbiter"])
parser.add_argument("type", choices=["bus-arbiter", "core-fsm"])
cli.main_parser(parser)

args = parser.parse_args()
if args.type == "arbiter":
mem = Memory(width=16, depth=256)
dut = Arbiter(rdport=mem.read_port(transparent=False),
wrport=mem.write_port())

if args.type == "bus-arbiter":
dut = BusArbiter()
ports = (
dut.i_win, dut.i_ra, dut.i_rb, dut.i_rsd, dut.i_ptr, dut.i_data,
dut.o_data,
dut.ctrl.ptr, dut.ctrl.reg, dut.ctrl.we,
dut.i_pc, dut.i_w, dut.i_ra, dut.i_rb, dut.i_rsd, dut.i_ptr,
dut.i_data, dut.o_data,
dut.c_mode.addr, dut.c_mode.reg, dut.c_mode.op,
dut.o_bus_addr,
dut.i_mem_data, dut.o_mem_re, dut.o_mem_data, dut.o_mem_we,
dut.i_ext_data, dut.o_ext_re, dut.o_ext_data, dut.o_ext_we,
)

cli.main_runner(parser, args, dut, ports=ports)
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