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base repository: m-labs/nmigen
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  • 1 commit
  • 4 files changed
  • 1 contributor

Commits on Jul 3, 2019

  1. vendor: give names to IO buffer instances.

    Fixes #123.
    whitequark committed Jul 3, 2019
    Copy the full SHA
    33f2162 View commit details
Showing with 26 additions and 26 deletions.
  1. +8 −8 nmigen/vendor/lattice_ecp5.py
  2. +2 −2 nmigen/vendor/lattice_ice40.py
  3. +8 −8 nmigen/vendor/xilinx_7series.py
  4. +8 −8 nmigen/vendor/xilinx_spartan6.py
16 changes: 8 additions & 8 deletions nmigen/vendor/lattice_ecp5.py
Original file line number Diff line number Diff line change
@@ -261,7 +261,7 @@ def get_input(self, pin, port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
for bit in range(len(port)):
m.submodules += Instance("IB",
m.submodules[pin.name] = Instance("IB",
i_I=port[bit],
o_O=i[bit]
)
@@ -273,7 +273,7 @@ def get_output(self, pin, port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(port)):
m.submodules += Instance("OB",
m.submodules[pin.name] = Instance("OB",
i_I=o[bit],
o_O=port[bit]
)
@@ -285,7 +285,7 @@ def get_tristate(self, pin, port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(port)):
m.submodules += Instance("OBZ",
m.submodules[pin.name] = Instance("OBZ",
i_T=t,
i_I=o[bit],
o_O=port[bit]
@@ -299,7 +299,7 @@ def get_input_output(self, pin, port, attrs, invert):
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None)
for bit in range(len(port)):
m.submodules += Instance("BB",
m.submodules[pin.name] = Instance("BB",
i_T=t,
i_I=o[bit],
o_O=i[bit],
@@ -313,7 +313,7 @@ def get_diff_input(self, pin, p_port, n_port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules += Instance("IB",
m.submodules[pin.name] = Instance("IB",
i_I=p_port[bit],
o_O=i[bit]
)
@@ -325,7 +325,7 @@ def get_diff_output(self, pin, p_port, n_port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules += Instance("OB",
m.submodules[pin.name] = Instance("OB",
i_I=o[bit],
o_O=p_port[bit],
)
@@ -337,7 +337,7 @@ def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules += Instance("OBZ",
m.submodules[pin.name] = Instance("OBZ",
i_T=t,
i_I=o[bit],
o_O=p_port[bit],
@@ -351,7 +351,7 @@ def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules += Instance("BB",
m.submodules[pin.name] = Instance("BB",
i_T=t,
i_I=o[bit],
o_O=i[bit],
4 changes: 2 additions & 2 deletions nmigen/vendor/lattice_ice40.py
Original file line number Diff line number Diff line change
@@ -248,9 +248,9 @@ def get_oxor(a, invert):
io_args.append(("i", "OUTPUT_ENABLE", pin.oe))

if is_global_input:
m.submodules += Instance("SB_GB_IO", *io_args)
m.submodules[pin.name] = Instance("SB_GB_IO", *io_args)
else:
m.submodules += Instance("SB_IO", *io_args)
m.submodules[pin.name] = Instance("SB_IO", *io_args)

def get_input(self, pin, port, attrs, invert):
self._check_feature("single-ended input", pin, attrs,
16 changes: 8 additions & 8 deletions nmigen/vendor/xilinx_7series.py
Original file line number Diff line number Diff line change
@@ -239,7 +239,7 @@ def get_input(self, pin, port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
for bit in range(len(port)):
m.submodules += Instance("IBUF",
m.submodules[pin.name] = Instance("IBUF",
i_I=port[bit],
o_O=i[bit]
)
@@ -251,7 +251,7 @@ def get_output(self, pin, port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(port)):
m.submodules += Instance("OBUF",
m.submodules[pin.name] = Instance("OBUF",
i_I=o[bit],
o_O=port[bit]
)
@@ -263,7 +263,7 @@ def get_tristate(self, pin, port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(port)):
m.submodules += Instance("OBUFT",
m.submodules[pin.name] = Instance("OBUFT",
i_T=t,
i_I=o[bit],
o_O=port[bit]
@@ -277,7 +277,7 @@ def get_input_output(self, pin, port, attrs, invert):
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None)
for bit in range(len(port)):
m.submodules += Instance("IOBUF",
m.submodules[pin.name] = Instance("IOBUF",
i_T=t,
i_I=o[bit],
o_O=i[bit],
@@ -291,7 +291,7 @@ def get_diff_input(self, pin, p_port, n_port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules += Instance("IBUFDS",
m.submodules[pin.name] = Instance("IBUFDS",
i_I=p_port[bit], i_IB=n_port[bit],
o_O=i[bit]
)
@@ -303,7 +303,7 @@ def get_diff_output(self, pin, p_port, n_port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules += Instance("OBUFDS",
m.submodules[pin.name] = Instance("OBUFDS",
i_I=o[bit],
o_O=p_port[bit], o_OB=n_port[bit]
)
@@ -315,7 +315,7 @@ def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules += Instance("OBUFTDS",
m.submodules[pin.name] = Instance("OBUFTDS",
i_T=t,
i_I=o[bit],
o_O=p_port[bit], o_OB=n_port[bit]
@@ -329,7 +329,7 @@ def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules += Instance("IOBUFDS",
m.submodules[pin.name] = Instance("IOBUFDS",
i_T=t,
i_I=o[bit],
o_O=i[bit],
16 changes: 8 additions & 8 deletions nmigen/vendor/xilinx_spartan6.py
Original file line number Diff line number Diff line change
@@ -248,7 +248,7 @@ def get_input(self, pin, port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
for bit in range(len(port)):
m.submodules += Instance("IBUF",
m.submodules[pin.name] = Instance("IBUF",
i_I=port[bit],
o_O=i[bit]
)
@@ -260,7 +260,7 @@ def get_output(self, pin, port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(port)):
m.submodules += Instance("OBUF",
m.submodules[pin.name] = Instance("OBUF",
i_I=o[bit],
o_O=port[bit]
)
@@ -272,7 +272,7 @@ def get_tristate(self, pin, port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(port)):
m.submodules += Instance("OBUFT",
m.submodules[pin.name] = Instance("OBUFT",
i_T=t,
i_I=o[bit],
o_O=port[bit]
@@ -286,7 +286,7 @@ def get_input_output(self, pin, port, attrs, invert):
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None)
for bit in range(len(port)):
m.submodules += Instance("IOBUF",
m.submodules[pin.name] = Instance("IOBUF",
i_T=t,
i_I=o[bit],
o_O=i[bit],
@@ -300,7 +300,7 @@ def get_diff_input(self, pin, p_port, n_port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules += Instance("IBUFDS",
m.submodules[pin.name] = Instance("IBUFDS",
i_I=p_port[bit], i_IB=n_port[bit],
o_O=i[bit]
)
@@ -312,7 +312,7 @@ def get_diff_output(self, pin, p_port, n_port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules += Instance("OBUFDS",
m.submodules[pin.name] = Instance("OBUFDS",
i_I=o[bit],
o_O=p_port[bit], o_OB=n_port[bit]
)
@@ -324,7 +324,7 @@ def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules += Instance("OBUFTDS",
m.submodules[pin.name] = Instance("OBUFTDS",
i_T=t,
i_I=o[bit],
o_O=p_port[bit], o_OB=n_port[bit]
@@ -338,7 +338,7 @@ def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules += Instance("IOBUFDS",
m.submodules[pin.name] = Instance("IOBUFDS",
i_T=t,
i_I=o[bit],
o_O=i[bit],