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base repository: m-labs/nmigen
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base: c8e92c0612ed
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head repository: m-labs/nmigen
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compare: 97af26664549
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Apr 22, 2019

  1. Copy the full SHA
    97af266 View commit details
Showing with 7 additions and 2 deletions.
  1. +7 −2 nmigen/back/verilog.py
9 changes: 7 additions & 2 deletions nmigen/back/verilog.py
Original file line number Diff line number Diff line change
@@ -11,7 +11,7 @@ class YosysError(Exception):
pass


def convert(*args, **kwargs):
def convert(*args, strip_src=False, **kwargs):
try:
popen = subprocess.Popen([os.getenv("YOSYS", "yosys"), "-q", "-"],
stdin=subprocess.PIPE,
@@ -26,6 +26,10 @@ def convert(*args, **kwargs):
raise YosysError("Could not find Yosys in PATH. Place `yosys` in PATH or specify "
"path explicitly via the YOSYS environment variable") from e

attr_map = []
if strip_src:
attr_map.append("-remove src")

il_text = rtlil.convert(*args, **kwargs)
verilog_text, error = popen.communicate("""
# Convert nMigen's RTLIL to readable Verilog.
@@ -37,8 +41,9 @@ def convert(*args, **kwargs):
proc_dff
proc_clean
memory_collect
attrmap {}
write_verilog -norename
""".format(il_text))
""".format(il_text, " ".join(attr_map)))
if popen.returncode:
raise YosysError(error.strip())
else: