back.verilog: allow stripping the src attribute, for cleaner output.

m-labs · Apr 22, 2019 · 9b26c31 · 9b26c31
1 parent 93d15ab
commit 9b26c31
Showing 1 changed file with 7 additions and 2 deletions.
diff --git a/nmigen/back/verilog.py b/nmigen/back/verilog.py
@@ -11,7 +11,7 @@ class YosysError(Exception):
     pass
 
 
-def convert(*args, **kwargs):
+def convert(*args, strip_src=False, **kwargs):
     try:
         popen = subprocess.Popen([os.getenv("YOSYS", "yosys"), "-q", "-"],
             stdin=subprocess.PIPE,
@@ -26,6 +26,10 @@ def convert(*args, **kwargs):
             raise YosysError("Could not find Yosys in PATH. Place `yosys` in PATH or specify "
                              "path explicitly via the YOSYS environment variable") from e
 
+    attr_map = []
+    if strip_src:
+        attr_map.append("-remove src")
+
     il_text = rtlil.convert(*args, **kwargs)
     verilog_text, error = popen.communicate("""
 # Convert nMigen's RTLIL to readable Verilog.
@@ -37,8 +41,9 @@ def convert(*args, **kwargs):
 proc_dff
 proc_clean
 memory_collect
+attrmap {}
 write_verilog -norename
-""".format(il_text))
+""".format(il_text, " ".join(attr_map)))
     if popen.returncode:
         raise YosysError(error.strip())
     else: