Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Multiple values in case statements #103

Closed
whitequark opened this issue Jun 14, 2019 · 0 comments
Closed

Multiple values in case statements #103

whitequark opened this issue Jun 14, 2019 · 0 comments
Labels
Milestone

Comments

@whitequark
Copy link
Contributor

Previously, I misunderstood an RTLIL feature where multiple values can be supplied for a case, like case 2'00, 2'01. In fact that means "any of these values", and it maps very nicely to Verilog too. So, maybe we could have with m.Case(0b00, 0b01): as well.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Projects
None yet
Development

No branches or pull requests

1 participant