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Previously, I misunderstood an RTLIL feature where multiple values can be supplied for a case, like case 2'00, 2'01. In fact that means "any of these values", and it maps very nicely to Verilog too. So, maybe we could have with m.Case(0b00, 0b01): as well.
The text was updated successfully, but these errors were encountered:
Previously, I misunderstood an RTLIL feature where multiple values can be supplied for a
case
, likecase 2'00, 2'01
. In fact that means "any of these values", and it maps very nicely to Verilog too. So, maybe we could havewith m.Case(0b00, 0b01):
as well.The text was updated successfully, but these errors were encountered: