Simulation-synthesis mismatch overriding value selected in a switch with a plain assignment #155

whitequark · 2019-07-18T08:12:10Z

Repro:

from nmigen import *
from nmigen.back.pysim import *
from nmigen.back.rtlil import *


class Bug(Elaboratable):
    def __init__(self):
        self.i = Signal()
        self.o = Signal()

    def elaborate(self, platform):
        m = Module()
        with m.If(self.i):
            m.d.comb += self.o.eq(1)
        m.d.comb += self.o.eq(0)
        return m


if __name__ == "__main__":
    bug = Bug()
    with Simulator(bug) as sim:
        def process():
            yield bug.i.eq(1)
            yield Delay(1e-6)
            print("o =", (yield bug.o))
        sim.add_process(process)
        sim.run()
    with open("bug.il", "w") as f:
        f.write(convert(bug))

$ python3 bug.py
o = 0
$ yosys bug.il -p "proc; eval -set i 1 -show o"
Eval result: \o = 1'1.

The reason is because the following generated RTLIL (edited for clarity):

module \top
  wire width 1 input 0 \i
  wire width 1 \o
  process $group_0
    assign \o 1'0
    switch { \i }
      case 1'1
        assign \o 1'1
    end
    assign \o 1'0
  end
end

is actually transformed to the following on parsing:

module \top
  wire width 1 input 0 \i
  wire width 1 \o
  process $group_0
    assign \o 1'0
    assign \o 1'0
    switch { \i }
      case 1'1
        assign \o 1'1
    end
  end
end

The best way to fix this would be to adjust RTLIL so this doesn't happen. The second best way to fix this (and remain compatible with Yosys 0.9) is to adjust the emitted RTLIL so it looks like this:

module \top
  wire width 1 input 0 \i
  wire width 1 \o
  process $group_0
    assign \o 1'0
    switch { \i }
      case 1'1
        assign \o 1'1
    end
    switch { }
      case
        assign \o 1'0
    end
  end
end

This results in slightly uglier Verilog:

module top(i);
  input i;
  reg o;
  always @* begin
    o = 1'h0;
    casez (i)
      1'h1:
          o = 1'h1;
    endcase
    begin
        o = 1'h0;
    end
  end
endmodule

The text was updated successfully, but these errors were encountered:

whitequark added bug backend:RTLIL labels Jul 18, 2019

whitequark added this to the 0.1 milestone Jul 18, 2019

whitequark closed this as completed in ee03eab Aug 3, 2019

nmigen-issue-migration mentioned this issue Jan 27, 2020

Simulation-synthesis mismatch overriding value selected in a switch with a plain assignment amaranth-lang/amaranth#156

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Simulation-synthesis mismatch overriding value selected in a switch with a plain assignment #155

Simulation-synthesis mismatch overriding value selected in a switch with a plain assignment #155

whitequark commented Jul 18, 2019 •

edited

Simulation-synthesis mismatch overriding value selected in a switch with a plain assignment #155

Simulation-synthesis mismatch overriding value selected in a switch with a plain assignment #155

Comments

whitequark commented Jul 18, 2019 • edited

whitequark commented Jul 18, 2019 •

edited