You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
The reason is because the following generated RTLIL (edited for clarity):
module \top
wire width 1 input 0 \i
wire width 1 \o
process $group_0
assign \o 1'0
switch { \i }
case 1'1
assign \o 1'1
end
assign \o 1'0
end
end
is actually transformed to the following on parsing:
module \top
wire width 1 input 0 \i
wire width 1 \o
process $group_0
assign \o 1'0
assign \o 1'0
switch { \i }
case 1'1
assign \o 1'1
end
end
end
The best way to fix this would be to adjust RTLIL so this doesn't happen. The second best way to fix this (and remain compatible with Yosys 0.9) is to adjust the emitted RTLIL so it looks like this:
module \top
wire width 1 input 0 \i
wire width 1 \o
process $group_0
assign \o 1'0
switch { \i }
case 1'1
assign \o 1'1
end
switch { }
case
assign \o 1'0
end
end
end
This results in slightly uglier Verilog:
module top(i);
input i;
reg o;
always @* begin
o = 1'h0;
casez (i)
1'h1:
o = 1'h1;
endcase
begin
o = 1'h0;
end
end
endmodule
The text was updated successfully, but these errors were encountered:
Repro:
The reason is because the following generated RTLIL (edited for clarity):
is actually transformed to the following on parsing:
The best way to fix this would be to adjust RTLIL so this doesn't happen. The second best way to fix this (and remain compatible with Yosys 0.9) is to adjust the emitted RTLIL so it looks like this:
This results in slightly uglier Verilog:
The text was updated successfully, but these errors were encountered: