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CEInserter does not work on memory ports #154

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Fatsie opened this issue Jul 17, 2019 · 1 comment
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CEInserter does not work on memory ports #154

Fatsie opened this issue Jul 17, 2019 · 1 comment
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@Fatsie
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Fatsie commented Jul 17, 2019

I was trying to make a memory that does not read on each clock cycle. I tried using CEInserter() for that but that does not seem to work. Following code show the problem. In generated verilog ce signal is never used.

#!/bin/env python3
from nmigen import *
from nmigen.lib.io import *
from nmigen.cli import main

class MemCE(Elaboratable):
    def __init__(self, width, depth):
        self.addr = Signal(max=depth)
        self.data = Pin(width, "io")
        self.write_en = Signal(1)
        self.ce = Signal(1)

        ##

        self._width = width
        self._depth = depth

    def elaborate(self, platform):
        m = Module()

        mem = Memory(self._width, self._depth)

        m.submodules.read_port = rp = CEInserter(self.ce)(mem.read_port())
        m.submodules.write_port = wp = CEInserter(self.ce)(mem.write_port())

        m.d.comb += [
            rp.addr.eq(self.addr),
            self.data.o.eq(rp.data),
            self.data.oe.eq(Const(1)),
            wp.addr.eq(self.addr),
            wp.data.eq(self.data.i),
            wp.en.eq(self.write_en),
        ]

        return m


f = MemCE(8, 1024)
main(f, ports=[f.addr, f.data.i, f.data.o, f.write_en, f.ce])

I do think this is a real problem, for example a block with a register file inside on which one uses CEInserter().

@whitequark whitequark added the bug label Jul 17, 2019
@whitequark whitequark added this to the 0.1 milestone Jul 17, 2019
@whitequark
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Yes, certainly a real problem. I think I considered it before but it slipped through.

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