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I was trying to make a memory that does not read on each clock cycle. I tried using CEInserter() for that but that does not seem to work. Following code show the problem. In generated verilog ce signal is never used.
I was trying to make a memory that does not read on each clock cycle. I tried using CEInserter() for that but that does not seem to work. Following code show the problem. In generated verilog ce signal is never used.
I do think this is a real problem, for example a block with a register file inside on which one uses CEInserter().
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