from nmigen import Module, Memory, Signal
from nmigen.back import pysim

def test_mem():
    m = Module()
    mem = Memory(8, 32)
    m.submodules.wrport = wrport = mem.write_port()
    ctr = Signal(4)
    m.d.sync += [
        wrport.data.eq(ctr + 0x30),
        wrport.addr.eq(ctr),
        wrport.en.eq(1),
        ctr.eq(ctr + 1),
    ]

    vcdf = open("membug.vcd", "w")
    with pysim.Simulator(m, vcd_file=vcdf) as sim:
        def testbench():
            for _ in range(5):
                yield
            for idx in range(5):
                print(idx, ":", hex((yield mem[idx])))
        sim.add_clock(1e-6)
        sim.add_sync_process(testbench())
        sim.run()

if __name__ == "__main__":
    test_mem()