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base repository: m-labs/nmigen
base: b0bd7bfaca2a
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head repository: m-labs/nmigen
compare: c49211c76ab1
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  • 3 commits
  • 6 files changed
  • 1 contributor

Commits on Dec 21, 2018

  1. back.rtlil: more consistent prefixing for subfragment port wires.

    whitequark committed Dec 21, 2018
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  2. hdl.mem: tie rdport.en high for asynchronous or transparent ports.

    whitequark committed Dec 21, 2018
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  3. hdl.mem: add tests for all error conditions.

    whitequark committed Dec 21, 2018
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