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base repository: m-labs/nmigen
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base: ae3c5834ed84
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head repository: m-labs/nmigen
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compare: d78e6c155b6d
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  • 1 commit
  • 2 files changed
  • 1 contributor

Commits on Jan 1, 2019

  1. Copy the full SHA
    d78e6c1 View commit details
Showing with 45 additions and 1 deletion.
  1. +27 −1 nmigen/hdl/mem.py
  2. +18 −0 nmigen/test/test_hdl_mem.py
28 changes: 27 additions & 1 deletion nmigen/hdl/mem.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@
from .ir import Instance


__all__ = ["Memory"]
__all__ = ["Memory", "ReadPort", "WritePort", "DummyPort"]


class Memory:
@@ -179,3 +179,29 @@ def get_fragment(self, platform):
for signal in self.memory._array:
f.add_driver(signal, self.domain)
return f


class DummyPort:
"""Dummy memory port.
This port can be used in place of either a read or a write port for testing and verification.
It does not include any read/write port specific attributes, i.e. none besides ``"domain"``;
any such attributes may be set manually.
"""
def __init__(self, width, addr_bits, domain="sync", name=None, granularity=None):
self.domain = domain

if granularity is None:
granularity = width
if name is None:
try:
name = tracer.get_var_name(depth=2)
except tracer.NameNotFound:
name = "dummy"

self.addr = Signal(addr_bits,
name="{}_addr".format(name))
self.data = Signal(width,
name="{}_data".format(name))
self.en = Signal(width // granularity,
name="{}_en".format(name))
18 changes: 18 additions & 0 deletions nmigen/test/test_hdl_mem.py
Original file line number Diff line number Diff line change
@@ -107,3 +107,21 @@ def test_write_port_granularity_wrong(self):
with self.assertRaises(ValueError,
msg="Write port granularity must divide memory width evenly"):
mem.write_port(granularity=3)


class DummyPortTestCase(FHDLTestCase):
def test_name(self):
p1 = DummyPort(width=8, addr_bits=2)
self.assertEqual(p1.addr.name, "p1_addr")
p2 = [DummyPort(width=8, addr_bits=2)][0]
self.assertEqual(p2.addr.name, "dummy_addr")
p3 = DummyPort(width=8, addr_bits=2, name="foo")
self.assertEqual(p3.addr.name, "foo_addr")

def test_sizes(self):
p1 = DummyPort(width=8, addr_bits=2)
self.assertEqual(p1.addr.nbits, 2)
self.assertEqual(p1.data.nbits, 8)
self.assertEqual(p1.en.nbits, 1)
p2 = DummyPort(width=8, addr_bits=2, granularity=2)
self.assertEqual(p2.en.nbits, 4)