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This is currently not done because of a quirk (bug?) in Yosys: YosysHQ/yosys#760. This is not right and affects user designs as the en signal is a constant and cannot be assigned to:
This is currently not done because of a quirk (bug?) in Yosys: YosysHQ/yosys#760. This is not right and affects user designs as the
en
signal is a constant and cannot be assigned to:nmigen/nmigen/hdl/mem.py
Lines 89 to 92 in d78e6c1
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