Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Support transparent ports with RE #16

Open
whitequark opened this issue Jan 1, 2019 · 0 comments
Open

Support transparent ports with RE #16

whitequark opened this issue Jan 1, 2019 · 0 comments
Labels
bug upstream

Comments

@whitequark
Copy link
Contributor

This is currently not done because of a quirk (bug?) in Yosys: YosysHQ/yosys#760. This is not right and affects user designs as the en signal is a constant and cannot be assigned to:

nmigen/nmigen/hdl/mem.py

Lines 89 to 92 in d78e6c1

if synchronous and not transparent:
self.en = Signal(name="{}_r_en".format(memory.name))
else:
self.en = Const(1)
.
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
bug upstream
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
1 participant
@whitequark