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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 935bf2d8cff6
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Jan 16, 2019

  1. back.rtlil: rename \sig$next to $next$sig.

    These used to serve a useful purpose being public, back when the RTLIL
    backend was immature. Not anymore; now they merely clutter up views
    in gtkwave and so on.
    whitequark committed Jan 16, 2019
    Copy the full SHA
    935bf2d View commit details
Showing with 8 additions and 5 deletions.
  1. +8 −5 nmigen/back/rtlil.py
13 changes: 8 additions & 5 deletions nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
@@ -7,6 +7,9 @@
from ..hdl import ast, ir, mem, xfrm


__all__ = ["convert"]


class _Namer:
def __init__(self):
super().__init__()
@@ -259,7 +262,7 @@ def resolve(self, signal, prefix=None):
port_id=port_id, port_kind=port_kind,
src=src(signal.src_loc))
if signal in self.driven:
wire_next = self.rtlil.wire(width=signal.nbits, name=wire_curr + "$next",
wire_next = self.rtlil.wire(width=signal.nbits, name="$next$" + wire_curr,
src=src(signal.src_loc))
else:
wire_next = None
@@ -667,7 +670,7 @@ def convert_fragment(builder, fragment, name, top):
verilog_trigger_sync_emitted = False

# Register all signals driven in the current fragment. This must be done first, as it
# affects further codegen; e.g. whether sig$next signals will be generated and used.
# affects further codegen; e.g. whether $next$sig signals will be generated and used.
for domain, signal in fragment.iter_drivers():
compiler_state.add_driven(signal, sync=domain is not None)

@@ -751,8 +754,8 @@ def convert_fragment(builder, fragment, name, top):

with module.process(name="$group_{}".format(group)) as process:
with process.case() as case:
# For every signal in comb domain, assign \sig$next to the reset value.
# For every signal in sync domains, assign \sig$next to the current
# For every signal in comb domain, assign $next$sig to the reset value.
# For every signal in sync domains, assign $next$sig to the current
# value (\sig).
for domain, signal in fragment.iter_drivers():
if signal not in group_signals:
@@ -794,7 +797,7 @@ def convert_fragment(builder, fragment, name, top):
sync.update(verilog_trigger, "1'0")
verilog_trigger_sync_emitted = True

# For every signal in every domain, assign \sig to \sig$next. The sensitivity list,
# For every signal in every domain, assign \sig to $next$sig. The sensitivity list,
# however, differs between domains: for comb domains, it is `always`, for sync
# domains with sync reset, it is `posedge clk`, for sync domains with async reset
# it is `posedge clk or posedge rst`.