whitequark · Dec 26, 2018 · Dec 27, 2018
diff --git a/boneless/arch/__init__.py b/boneless/arch/__init__.py
diff --git a/boneless/disasm.py → boneless/arch/disasm.py b/boneless/disasm.py → boneless/arch/disasm.py
diff --git a/boneless/instr.py → boneless/arch/instr.py b/boneless/instr.py → boneless/arch/instr.py
diff --git a/boneless/opcode.py → boneless/arch/opcode.py b/boneless/opcode.py → boneless/arch/opcode.py
diff --git a/boneless/gateware/core_fsm.py b/boneless/gateware/core_fsm.py
diff --git a/boneless/gateware/formal.py b/boneless/gateware/formal.py
@@ -5,7 +5,10 @@
 
 
 class BonelessFormalInterface:
-    def __init__(self):
+    def __init__(self, mem_wrport=None, ext_port=None):
+        self.mem_wrport = mem_wrport
+        self.ext_port   = ext_port
+
         # Active when an instruction is retired.
         self.stb        = Signal(    name="fi_stb")
         # Retired instruction and its PC.
@@ -32,3 +35,21 @@ def __init__(self):
             self.mem_w_en, self.mem_w_addr, self.mem_w_data,
             self.ext_addr, self.ext_r_data, self.ext_r_en, self.ext_w_data, self.ext_w_en
         ]
+
+    def get_fragment(self, platform):
+        m = Module()
+        if self.mem_wrport:
+            m.d.comb += [
+                self.mem_w_addr.eq(self.mem_wrport.addr),
+                self.mem_w_data.eq(self.mem_wrport.data),
+                self.mem_w_en  .eq(self.mem_wrport.en),
+            ]
+        if self.ext_port:
+            m.d.comb += [
+                self.ext_addr  .eq(self.ext_port.addr),
+                self.ext_r_data.eq(self.ext_port.r_data),
+                self.ext_r_en  .eq(self.ext_port.r_en),
+                self.ext_w_data.eq(self.ext_port.w_data),
+                self.ext_w_en  .eq(self.ext_port.w_en),
+            ]
+        return m.lower(platform)
diff --git a/boneless/test/__init__.py b/boneless/test/__init__.py
diff --git a/boneless/gateware/test_core.py → boneless/test/test_core.py b/boneless/gateware/test_core.py → boneless/test/test_core.py
@@ -1,17 +1,21 @@
 import unittest
 import functools
-from nmigen.compat import *
+from nmigen import *
+from nmigen.back.pysim import *
 
-from ..instr import *
-from .core_fsm import BonelessCoreFSM, _StubMemoryPort
+from ..arch.instr import *
+from ..gateware.core_fsm import BonelessCoreFSM, _ExternalPort
 
 
 def simulation_test(**kwargs):
     def configure_wrapper(case):
         @functools.wraps(case)
         def wrapper(self):
             self.configure(self.tb, **kwargs)
-            run_simulation(self.tb, case(self, self.tb), vcd_name="test.vcd")
+            with Simulator(self.tb) as sim:
+                sim.add_clock(1e-6)
+                sim.add_sync_process(case(self, self.tb))
+                sim.run()
         return wrapper
     return configure_wrapper
 
@@ -21,29 +25,36 @@ def __init__(self):
         self.mem_init = []
         self.ext_init = []
 
-    def do_finalize(self):
-        self.mem = Memory(width=16, depth=len(self.mem_init), init=self.mem_init)
-        self.specials.mem = self.mem
+    def get_fragment(self, platform):
+        m = Module()
 
-        mem_rdport = self.mem.get_port(has_re=True, mode=READ_FIRST)
-        mem_wrport = self.mem.get_port(write_capable=True)
-        self.specials.mem_r = mem_rdport
-        self.specials.mem_w = mem_wrport
+        mem = self.mem = Memory(width=16, depth=len(self.mem_init), init=self.mem_init)
+        m.submodules.mem_rdport = mem_rdport = mem.read_port(transparent=False)
+        m.submodules.mem_wrport = mem_wrport = mem.write_port()
 
         if self.ext_init:
-            self.ext = Memory(width=16, depth=len(self.ext_init), init=self.ext_init)
-            self.specials.ext = self.ext
-
-            ext_port = self.ext.get_port(has_re=True, write_capable=True)
-            self.specials.ext_rw = ext_port
+            ext = self.ext = Memory(width=16, depth=len(self.ext_init), init=self.ext_init)
+            m.submodules.ext_rdport = ext_rdport = ext.read_port(transparent=False)
+            m.submodules.ext_wrport = ext_wrport = ext.write_port()
+
+            ext_port = _ExternalPort()
+            m.d.comb += [
+                ext_rdport.addr.eq(ext_port.addr),
+                ext_port.r_data.eq(ext_rdport.data),
+                ext_rdport.en.eq(ext_port.r_en),
+                ext_wrport.addr.eq(ext_port.addr),
+                ext_wrport.data.eq(ext_port.w_data),
+                ext_wrport.en.eq(ext_port.w_en),
+            ]
         else:
-            ext_port = _StubMemoryPort("ext")
-            self.submodules.ext_rw = ext_port
+            ext_port = None
 
-        self.submodules.dut = BonelessCoreFSM(reset_addr=8,
+        m.submodules.dut = self.dut = BonelessCoreFSM(reset_addr=8,
             mem_rdport=mem_rdport,
             mem_wrport=mem_wrport,
-            ext_port=ext_port)
+            ext_port  =ext_port)
+
+        return m.lower(platform)
 
 
 class BonelessTestCase(unittest.TestCase):
@@ -55,7 +66,7 @@ def configure(self, tb, code, regs=[], data=[], extr=[]):
         tb.ext_init = extr
 
     def run_core(self, tb):
-        while (yield tb.dut.s_insn) != J(-1)[0]:
+        while not (yield tb.dut.halted):
             yield
 
     def assertMemory(self, tb, addr, value):

diff --git a/boneless/test_disasm.py → boneless/test/test_disasm.py b/boneless/test_disasm.py → boneless/test/test_disasm.py
@@ -1,7 +1,7 @@
 import unittest
 
-from .disasm import disassemble
-from .instr import *
+from ..arch.instr import *
+from ..arch.disasm import disassemble
 
 
 class DisassemblerTestCase(unittest.TestCase):

diff --git a/examples/run.sh b/examples/run.sh
@@ -1,7 +1,7 @@
 #!/bin/sh -ex
 
 cd $(dirname $0)
-python3 -W ignore -m boneless.gateware.core_fsm pins generate fsm_core_pins.v
+python3 -m boneless.gateware.core_fsm pins generate fsm_core_pins.v
 yosys fsm_core_pins.v iceblink.sv -p "synth_ice40 -top top -json iceblink.json"
 nextpnr-ice40 --hx1k --package vq100 --pcf iceblink.pcf --json iceblink.json --asc iceblink.txt
 icepack iceblink.txt iceblink.bin

diff --git a/formal/formal.sv b/formal/formal.sv
@@ -46,17 +46,17 @@ module boneless_formal(
         .rst(0),
         .clk(clk),
         .r_win(r_win),
-        .mem_r_adr(mem_r_addr),
-        .mem_r_dat_r(mem_r_data),
-        .mem_r_re(mem_r_en),
-        .mem_w_adr(mem_w_addr),
-        .mem_w_dat_w(mem_w_data),
-        .mem_w_we(mem_w_en),
-        .ext_adr(ext_addr),
-        .ext_dat_r(ext_r_data),
-        .ext_re(ext_r_en),
-        .ext_dat_w(ext_w_data),
-        .ext_we(ext_w_en),
+        .mem_r_addr(mem_r_addr),
+        .mem_r_data(mem_r_data),
+        .mem_r_en(mem_r_en),
+        .mem_w_addr(mem_w_addr),
+        .mem_w_data(mem_w_data),
+        .mem_w_en(mem_w_en),
+        .ext_addr(ext_addr),
+        .ext_r_data(ext_r_data),
+        .ext_r_en(ext_r_en),
+        .ext_w_data(ext_w_data),
+        .ext_w_en(ext_w_en),
         .fi_stb(fi_stb),
         .fi_pc(fi_pc),
         .fi_flags(fi_flags),

diff --git a/formal/run.sh b/formal/run.sh
@@ -1,5 +1,5 @@
 #!/bin/sh -e
 
 cd $(dirname $0)
-python3 -W ignore -m boneless.gateware.core_fsm formal generate fsm_core_fi.v
+python3 -m boneless.gateware.core_fsm formal generate fsm_core_fi.v
 sby -f -d workdir fsm_formal.sby