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base repository: m-labs/nmigen
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base: 470d66934f9b
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head repository: m-labs/nmigen
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compare: 3ea35b8566e4
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  • 1 commit
  • 2 files changed
  • 1 contributor

Commits on Dec 27, 2018

  1. Copy the full SHA
    3ea35b8 View commit details
Showing with 13 additions and 11 deletions.
  1. +3 −4 nmigen/lib/coding.py
  2. +10 −7 nmigen/test/test_lib_coding.py
7 changes: 3 additions & 4 deletions nmigen/lib/coding.py
Original file line number Diff line number Diff line change
@@ -69,7 +69,7 @@ def get_fragment(self, platform):
m = Module()
for j, b in enumerate(reversed(self.i)):
with m.If(b):
m.d.comb += self.o.eq(j)
m.d.comb += self.o.eq(len(self.i) - j - 1)
m.d.comb += self.n.eq(self.i == 0)
return m.lower(platform)

@@ -105,9 +105,8 @@ def get_fragment(self, platform):
for j in range(len(self.o)):
with m.Case(j):
m.d.comb += self.o.eq(1 << j)
with m.Case():
with m.If(self.n):
m.d.comb += self.o.eq(0)
with m.If(self.n):
m.d.comb += self.o.eq(0)
return m.lower(platform)


17 changes: 10 additions & 7 deletions nmigen/test/test_lib_coding.py
Original file line number Diff line number Diff line change
@@ -28,6 +28,7 @@ def process():
self.assertEqual((yield enc.o), 0)

sim.add_process(process)
sim.run()


class PriorityEncoderTestCase(FHDLTestCase):
@@ -54,25 +55,27 @@ def process():
self.assertEqual((yield enc.o), 1)

sim.add_process(process)
sim.run()


class DecoderTestCase(FHDLTestCase):
def test_basic(self):
dec = Decoder(4)
with Simulator(dec) as sim:
def process():
self.assertEqual((yield enc.o), 0b0001)
self.assertEqual((yield dec.o), 0b0001)

yield enc.i.eq(1)
yield dec.i.eq(1)
yield Delay()
self.assertEqual((yield enc.o), 0b0010)
self.assertEqual((yield dec.o), 0b0010)

yield enc.i.eq(3)
yield dec.i.eq(3)
yield Delay()
self.assertEqual((yield enc.o), 0b1000)
self.assertEqual((yield dec.o), 0b1000)

yield enc.n.eq(1)
yield dec.n.eq(1)
yield Delay()
self.assertEqual((yield enc.o), 0b0000)
self.assertEqual((yield dec.o), 0b0000)

sim.add_process(process)
sim.run()