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base repository: whitequark/glasgow
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head repository: whitequark/glasgow
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compare: ce028fca23c4
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  • 3 commits
  • 9 files changed
  • 1 contributor

Commits on Mar 8, 2019

  1. support.bits: rewrite Bitfield around bitarray instead of ctypes

    @marcan
    marcan committed Mar 8, 2019
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    7444bc7 View commit details

  2. support.bits: specify total Bitfield width in bits & fix all callsites

    @marcan
    marcan committed Mar 8, 2019
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    d5e57a2 View commit details

  3. support.bits: add len() support for Bitfield (returns total bit width)

    @marcan
    marcan committed Mar 8, 2019
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    ce028fc View commit details
2 changes: 1 addition & 1 deletion software/glasgow/arch/arc/core.py
View file
Original file line number Diff line number Diff line change
@@ -25,7 +25,7 @@
AUX_AUX_USER_SP_addr = 0x0d
AUX_INT_VECTOR_BASE_addr = 0x25

AUX_STATUS32 = Bitfield("AUX_STATUS32", 4, [
AUX_STATUS32 = Bitfield("AUX_STATUS32", 32, [
("H", 1),
("E1", 1),
("E2", 1),
6 changes: 3 additions & 3 deletions software/glasgow/arch/arc/jtag.py
View file
Original file line number Diff line number Diff line change
@@ -30,7 +30,7 @@

# DR values

DR_STATUS = Bitfield("DR_STATUS", 1, [
DR_STATUS = Bitfield("DR_STATUS", 4, [
("ST", 1),
("FL", 1),
("RD", 1),
@@ -44,10 +44,10 @@
DR_TXN_COMMAND_READ_CORE = bitarray("1010", endian="little")
DR_TXN_COMMAND_READ_AUX = bitarray("0110", endian="little")

DR_ADDRESS = Bitfield("DR_ADDRESS", 4, [
DR_ADDRESS = Bitfield("DR_ADDRESS", 32, [
("Address", 32),
])

DR_DATA = Bitfield("DR_DATA", 4, [
DR_DATA = Bitfield("DR_DATA", 32, [
("Data", 32),
])
8 changes: 4 additions & 4 deletions software/glasgow/arch/arc/mec16xx.py
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Original file line number Diff line number Diff line change
@@ -17,7 +17,7 @@
"Flash_Config",
]

DR_RESET_TEST = Bitfield("DR_RESET_TEST", 4, [
DR_RESET_TEST = Bitfield("DR_RESET_TEST", 32, [
# Probably ME. It seems to work for me, but none of SMSC documents ever coherently point
# to a single DR with the ME bit *or* specify the location of the ME bit. Cursed.
("ME", 1),
@@ -40,7 +40,7 @@
Flash_Config_addr = Flash_base_addr + 0x110
Flash_Init_addr = Flash_base_addr + 0x114

Flash_Command = Bitfield("Flash_Command", 4, [
Flash_Command = Bitfield("Flash_Command", 32, [
("Flash_Mode", 2),
("Burst", 1),
("EC_Int", 1),
@@ -53,7 +53,7 @@
Flash_Mode_Program = 2
Flash_Mode_Erase = 3

Flash_Status = Bitfield("Flash_Status", 4, [
Flash_Status = Bitfield("Flash_Status", 32, [
("Busy", 1),
("Data_Full", 1),
("Address_Full", 1),
@@ -67,7 +67,7 @@
("Protect_Err", 1),
])

Flash_Config = Bitfield("Flash_Config", 4, [
Flash_Config = Bitfield("Flash_Config", 32, [
("Reg_Ctl_En", 1),
("Host_Ctl", 1),
("Boot_Lock", 1),
2 changes: 1 addition & 1 deletion software/glasgow/arch/jtag.py
View file
Original file line number Diff line number Diff line change
@@ -11,7 +11,7 @@
]


DR_IDCODE = Bitfield("DR_IDCODE", 4, [
DR_IDCODE = Bitfield("DR_IDCODE", 32, [
("present", 1),
("mfg_id", 11),
("part_id", 16),
8 changes: 4 additions & 4 deletions software/glasgow/arch/mips/core.py
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Original file line number Diff line number Diff line change
@@ -46,7 +46,7 @@

# CP0 Config layout

CP0_Config = Bitfield("CP0_Config", 4, [
CP0_Config = Bitfield("CP0_Config", 32, [
("K0", 3),
(None, 4),
("MT", 3),
@@ -92,7 +92,7 @@

# CP0 Config1 layout

CP0_Config1 = Bitfield("CP0_Config1", 4, [
CP0_Config1 = Bitfield("CP0_Config1", 32, [
("FP", 1),
("EP", 1),
("CA", 1),
@@ -112,7 +112,7 @@

# CP0 Debug layout

CP0_Debug = Bitfield("CP0_Debug", 4, [
CP0_Debug = Bitfield("CP0_Debug", 32, [
("DSS", 1),
("DBp", 1),
("DDBL", 1),
@@ -143,7 +143,7 @@

# CP0 Debug2 layout

CP0_Debug2 = Bitfield("CP0_Debug2", 4, [
CP0_Debug2 = Bitfield("CP0_Debug2", 32, [
("PaCo", 1),
("Tup", 1),
("DQ", 1),
14 changes: 7 additions & 7 deletions software/glasgow/arch/mips/ejtag.py
View file
Original file line number Diff line number Diff line change
@@ -43,7 +43,7 @@

# IMPCODE DR layout

DR_IMPCODE = Bitfield("DR_IMPCODE", 4, [
DR_IMPCODE = Bitfield("DR_IMPCODE", 32, [
("MIPS32_64", 1),
("TypeInfo", 10),
("Type", 3),
@@ -70,7 +70,7 @@

# CONTROL DR layout

DR_CONTROL = Bitfield("DR_CONTROL", 4, [
DR_CONTROL = Bitfield("DR_CONTROL", 32, [
(None, 3),
("DM", 1),
(None, 1),
@@ -141,7 +141,7 @@ def DRSEG_DBVn_addr_v1(n): return DRSEG_addr + 0x020c + 0x10 * n

# DRSEG DCR layout

DRSEG_DCR = Bitfield("DRSEG_DCR", 4, [
DRSEG_DCR = Bitfield("DRSEG_DCR", 32, [
("ProbEn", 1),
("SRstE", 1),
("NMIpend", 1),
@@ -173,7 +173,7 @@ def DRSEG_DBVn_addr_v1(n): return DRSEG_addr + 0x020c + 0x10 * n

# DRSEG IBS layout

DRSEG_IBS = Bitfield("DRSEG_IBS", 4, [
DRSEG_IBS = Bitfield("DRSEG_IBS", 32, [
("BS", 15),
("IBPshare", 1),
(None, 8),
@@ -185,7 +185,7 @@ def DRSEG_DBVn_addr_v1(n): return DRSEG_addr + 0x020c + 0x10 * n

# DRSEG IBC layout

DRSEG_IBC = Bitfield("DRSEG_IBC", 4, [
DRSEG_IBC = Bitfield("DRSEG_IBC", 32, [
("BE", 1),
(None, 1),
("TE", 1),
@@ -201,7 +201,7 @@ def DRSEG_DBVn_addr_v1(n): return DRSEG_addr + 0x020c + 0x10 * n

# DRSEG DBS layout

DRSEG_DBS = Bitfield("DRSEG_DBS", 4, [
DRSEG_DBS = Bitfield("DRSEG_DBS", 32, [
("BS", 15),
("DBPshare", 1),
(None, 8),
@@ -214,7 +214,7 @@ def DRSEG_DBVn_addr_v1(n): return DRSEG_addr + 0x020c + 0x10 * n

# DRSEG DBC layout

DRSEG_DBC = Bitfield("DRSEG_DBC", 4, [
DRSEG_DBC = Bitfield("DRSEG_DBC", 32, [
("BE", 1),
("IVM", 1),
("TE", 1),
6 changes: 3 additions & 3 deletions software/glasgow/arch/xilinx/xc9500xl.py
View file
Original file line number Diff line number Diff line change
@@ -36,19 +36,19 @@
IR_BYPASS = bitarray("11111111", endian="little") # BYPASS[1]


DR_ISDATA = Bitfield("DR_ISDATA", 5, [
DR_ISDATA = Bitfield("DR_ISDATA", 34, [
("valid", 1),
("strobe", 1),
("data", 32),
])

DR_ISADDRESS = Bitfield("DR_ISADDRESS", 3, [
DR_ISADDRESS = Bitfield("DR_ISADDRESS", 18, [
("valid", 1),
("strobe", 1),
("address", 16),
])

DR_ISCONFIGURATION = Bitfield("DR_ISCONFIGURATION", 7, [
DR_ISCONFIGURATION = Bitfield("DR_ISCONFIGURATION", 50, [
("valid", 1),
("strobe", 1),
("data", 32),
18 changes: 9 additions & 9 deletions software/glasgow/protocol/sfdp.py
View file
Original file line number Diff line number Diff line change
@@ -24,7 +24,7 @@ def jedec_revision(self):
return "unknown JESD216 revision"


_JEDEC_Flash_Param_0 = Bitfield("JEDEC_Flash_Param_0", 4, [
_JEDEC_Flash_Param_0 = Bitfield("JEDEC_Flash_Param_0", 32, [
("block_sector_erase_size", 2),
("write_granularity", 1),
("volatile_wren_required", 1),
@@ -40,12 +40,12 @@ def jedec_revision(self):
(None, 9),
])

_JEDEC_Flash_Param_1 = Bitfield("JEDEC_Flash_Param_1", 4, [
_JEDEC_Flash_Param_1 = Bitfield("JEDEC_Flash_Param_1", 32, [
("density_value", 31),
("density_over_2gbit", 1),
])

_JEDEC_Flash_Param_2 = Bitfield("JEDEC_Flash_Param_2", 4, [
_JEDEC_Flash_Param_2 = Bitfield("JEDEC_Flash_Param_2", 32, [
("_fast_read_1_4_4_wait_states", 5),
("_fast_read_1_4_4_mode_bits", 3),
("_fast_read_1_4_4_opcode", 8),
@@ -54,7 +54,7 @@ def jedec_revision(self):
("_fast_read_1_1_4_opcode", 8),
])

_JEDEC_Flash_Param_3 = Bitfield("JEDEC_Flash_Param_3", 4, [
_JEDEC_Flash_Param_3 = Bitfield("JEDEC_Flash_Param_3", 32, [
("_fast_read_1_1_2_wait_states", 5),
("_fast_read_1_1_2_mode_bits", 3),
("_fast_read_1_1_2_opcode", 8),
@@ -63,35 +63,35 @@ def jedec_revision(self):
("_fast_read_1_2_2_opcode", 8),
])

_JEDEC_Flash_Param_4 = Bitfield("JEDEC_Flash_Param_4", 4, [
_JEDEC_Flash_Param_4 = Bitfield("JEDEC_Flash_Param_4", 32, [
("has_2_2_2_fast_read", 1),
(None, 3),
("has_4_4_4_fast_read", 1),
(None, 27),
])

_JEDEC_Flash_Param_5 = Bitfield("JEDEC_Flash_Param_5", 4, [
_JEDEC_Flash_Param_5 = Bitfield("JEDEC_Flash_Param_5", 32, [
(None, 16),
("_fast_read_2_2_2_wait_states", 5),
("_fast_read_2_2_2_mode_bits", 3),
("_fast_read_2_2_2_opcode", 8),
])

_JEDEC_Flash_Param_6 = Bitfield("JEDEC_Flash_Param_6", 4, [
_JEDEC_Flash_Param_6 = Bitfield("JEDEC_Flash_Param_6", 32, [
(None, 16),
("_fast_read_4_4_4_wait_states", 5),
("_fast_read_4_4_4_mode_bits", 3),
("_fast_read_4_4_4_opcode", 8),
])

_JEDEC_Flash_Param_7 = Bitfield("JEDEC_Flash_Param_7", 4, [
_JEDEC_Flash_Param_7 = Bitfield("JEDEC_Flash_Param_7", 32, [
("sector_type_1_size", 8),
("sector_type_1_opcode", 8),
("sector_type_2_size", 8),
("sector_type_2_opcode", 8),
])

_JEDEC_Flash_Param_8 = Bitfield("JEDEC_Flash_Param_8", 4, [
_JEDEC_Flash_Param_8 = Bitfield("JEDEC_Flash_Param_8", 32, [
("sector_type_3_size", 8),
("sector_type_3_opcode", 8),
("sector_type_4_size", 8),
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