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base repository: m-labs/nmigen
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compare: a4183eba69f6
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Dec 21, 2018

  1. hdl.mem: use more informative signal naming for ports.

    whitequark committed Dec 21, 2018
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    a4183eb View commit details
Showing with 11 additions and 6 deletions.
  1. +11 −6 nmigen/hdl/mem.py
17 changes: 11 additions & 6 deletions nmigen/hdl/mem.py
Original file line number Diff line number Diff line change
@@ -68,10 +68,12 @@ def __init__(self, memory, domain, synchronous, transparent):
self.synchronous = synchronous
self.transparent = transparent

self.addr = Signal(max=memory.depth)
self.data = Signal(memory.width)
self.addr = Signal(max=memory.depth,
name="{}_r_addr".format(memory.name))
self.data = Signal(memory.width,
name="{}_r_data".format(memory.name))
if synchronous and not transparent:
self.en = Signal()
self.en = Signal(name="{}_r_en".format(memory.name))
else:
self.en = Const(1)

@@ -131,9 +133,12 @@ def __init__(self, memory, domain, priority, granularity):
self.priority = priority
self.granularity = granularity

self.addr = Signal(max=memory.depth)
self.data = Signal(memory.width)
self.en = Signal(memory.width // granularity)
self.addr = Signal(max=memory.depth,
name="{}_w_addr".format(memory.name))
self.data = Signal(memory.width,
name="{}_w_data".format(memory.name))
self.en = Signal(memory.width // granularity,
name="{}_w_en".format(memory.name))

def get_fragment(self, platform):
f = Instance("$memwr",