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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 913339c04a0d
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  • 1 commit
  • 2 files changed
  • 1 contributor

Commits on Dec 21, 2018

  1. hdl.ir: fix port propagation between siblings.

    whitequark committed Dec 21, 2018
    Copy the full SHA
    913339c View commit details
Showing with 20 additions and 3 deletions.
  1. +3 −3 nmigen/hdl/ir.py
  2. +17 −0 nmigen/test/test_hdl_ir.py
6 changes: 3 additions & 3 deletions nmigen/hdl/ir.py
Original file line number Diff line number Diff line change
@@ -270,9 +270,9 @@ def _propagate_ports(self, ports):

# Go through subfragments and refine our approximation for ports.
for subfrag, name in self.subfragments:
# Always ask subfragments to provide all signals we're using and signals we're asked
# to provide. If the subfragment is not driving it, it will silently ignore it.
sub_ins, sub_outs, sub_inouts = subfrag._propagate_ports(ports=self_used | ports)
# Always ask subfragments to provide all signals that are our inputs.
# If the subfragment is not driving it, it will silently ignore it.
sub_ins, sub_outs, sub_inouts = subfrag._propagate_ports(ports=ins | ports)
# Refine the input port approximation: if a subfragment is driving a signal,
# it is definitely not our input. But, if a subfragment requires a signal as an input,
# and we aren't driving it, it has to be our input as well.
17 changes: 17 additions & 0 deletions nmigen/test/test_hdl_ir.py
Original file line number Diff line number Diff line change
@@ -117,6 +117,23 @@ def test_output_from_subfragment(self):
(self.c2, "o"),
]))

def test_input_output_sibling(self):
f1 = Fragment()
f2 = Fragment()
f2.add_statements(
self.c1.eq(self.c2)
)
f1.add_subfragment(f2)
f3 = Fragment()
f3.add_statements(
self.c2.eq(0)
)
f3.add_driver(self.c2)
f1.add_subfragment(f3)

f1._propagate_ports(ports=())
self.assertEqual(f1.ports, SignalDict())

def test_input_cd(self):
sync = ClockDomain()
f = Fragment()