Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/nmigen
base: f6772759c8ad
Choose a base ref
...
head repository: m-labs/nmigen
compare: 6ee80408bbb5
Choose a head ref
  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Dec 22, 2018

  1. compat: fix confusing naming for memory port address signal.

    whitequark committed Dec 22, 2018
    Configuration menu
    Copy the full SHA
    5361b4c View commit details
    Browse the repository at this point in the history

  2. back.verilog: do not rename internal signals. 

    _0_ is not really any better than \$13, and the latter at least has
continuity between nMigen, RTLIL and Verilog.
    whitequark committed Dec 22, 2018
    Configuration menu
    Copy the full SHA
    6ee8040 View commit details
    Browse the repository at this point in the history