Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/nmigen
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: f6772759c8ad
Choose a base ref
...
head repository: m-labs/nmigen
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 6ee80408bbb5
Choose a head ref
  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Dec 22, 2018

  1. Copy the full SHA
    5361b4c View commit details
  2. back.verilog: do not rename internal signals.

    _0_ is not really any better than \$13, and the latter at least has
    continuity between nMigen, RTLIL and Verilog.
    whitequark committed Dec 22, 2018
    Copy the full SHA
    6ee8040 View commit details
Showing with 2 additions and 1 deletion.
  1. +1 −1 nmigen/back/verilog.py
  2. +1 −0 nmigen/compat/fhdl/specials.py
2 changes: 1 addition & 1 deletion nmigen/back/verilog.py
Original file line number Diff line number Diff line change
@@ -28,7 +28,7 @@ def convert(*args, **kwargs):
proc_dff
proc_clean
memory_collect
write_verilog
write_verilog -norename
# Make sure there are no undriven wires in generated RTLIL.
proc
select -assert-none w:* i:* %a %d o:* %a %ci* %d c:* %co* %a %d n:$* %d
1 change: 1 addition & 0 deletions nmigen/compat/fhdl/specials.py
Original file line number Diff line number Diff line change
@@ -64,6 +64,7 @@ def get_port(self, write_capable=False, async_read=False, has_re=False, we_granu
we_granularity = None
assert mode != NO_CHANGE
rdport = self.read_port(synchronous=not async_read, transparent=mode == WRITE_FIRST)
rdport.addr.name = "{}_addr".format(self.name)
adr = rdport.addr
dat_r = rdport.data
if write_capable: