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base repository: m-labs/nmigen
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base: c49211c76ab1
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head repository: m-labs/nmigen
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compare: a40e2cac4bb5
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Dec 21, 2018

  1. back.pysim: fix an issue with too few funclet slots.

    whitequark committed Dec 21, 2018
    Copy the full SHA
    a40e2ca View commit details
Showing with 3 additions and 4 deletions.
  1. +3 −4 nmigen/back/pysim.py
7 changes: 3 additions & 4 deletions nmigen/back/pysim.py
Original file line number Diff line number Diff line change
@@ -437,6 +437,8 @@ def add_signal(signal):
self._domain_signals[domain] = bitarray()
self._domain_signals[domain].append(False)

self._funclets.append(set())

self._domain_triggers.append(None)
if self._vcd_writer:
self._vcd_signals.append(set())
@@ -520,10 +522,7 @@ def add_domain_signal(signal, domain):
funclet = compiler(statements)

def add_funclet(signal, funclet):
signal_slot = self._signal_slots[signal]
while len(self._funclets) <= signal_slot:
self._funclets.append(set())
self._funclets[signal_slot].add(funclet)
self._funclets[self._signal_slots[signal]].add(funclet)

for signal in compiler.sensitivity:
add_funclet(signal, funclet)