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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
compare: 00ef7a78d38f
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  • 2 commits
  • 3 files changed
  • 1 contributor

Commits on Dec 21, 2018

  1. hdl.ir: do not flatten instances or collect ports from their statements. 

    This results in absurd behavior for memories.
    whitequark committed Dec 21, 2018
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  2. compat: provide verilog.convert shim.

    whitequark committed Dec 21, 2018
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