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whitequarkwhitequark
committedJan 14, 2019
Bulk port of all gateware to nMigen compatibility layer.
1 parent 52038d8 commit 1d8e1d0

39 files changed

+70
-91
lines changed
 

‎software/glasgow/access/__init__.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
from abc import ABCMeta, abstractmethod
2-
from migen import *
2+
from nmigen.compat import *
33

44
from ..gateware.pads import Pads
55

‎software/glasgow/access/direct/multiplexer.py

+1-1
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@@ -1,5 +1,5 @@
11
import logging
2-
from migen import *
2+
from nmigen.compat import *
33

44
from .. import AccessMultiplexer, AccessMultiplexerInterface
55

‎software/glasgow/access/simulation/demultiplexer.py

+1-1
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@@ -1,5 +1,5 @@
11
import asyncio
2-
from migen import *
2+
from nmigen.compat import *
33

44
from ...support.logging import *
55
from .. import AccessDemultiplexer, AccessDemultiplexerInterface

‎software/glasgow/access/simulation/multiplexer.py

+2-2
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@@ -1,5 +1,5 @@
1-
from migen import *
2-
from migen.genlib.fifo import _FIFOInterface, AsyncFIFO, SyncFIFOBuffered
1+
from nmigen.compat import *
2+
from nmigen.compat.genlib.fifo import _FIFOInterface, AsyncFIFO, SyncFIFOBuffered
33

44
from .. import AccessMultiplexer, AccessMultiplexerInterface
55
from ...gateware.fx2 import _FIFOWithFlush

‎software/glasgow/applet/__init__.py

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@@ -75,7 +75,7 @@ async def run(self, args):
7575
import threading
7676
import inspect
7777
import json
78-
from migen.sim import *
78+
from nmigen.compat.sim import *
7979

8080
from ..access.simulation import *
8181
from ..access.direct import *

‎software/glasgow/applet/benchmark/__init__.py

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@@ -2,7 +2,7 @@
22
import asyncio
33
import struct
44
import time
5-
from migen import *
5+
from nmigen.compat import *
66

77
from .. import *
88
from ...gateware.lfsr import *

‎software/glasgow/applet/hd44780/__init__.py

+2-2
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@@ -9,8 +9,8 @@
99
import math
1010
import argparse
1111
import logging
12-
from migen import *
13-
from migen.genlib.cdc import MultiReg
12+
from nmigen.compat import *
13+
from nmigen.compat.genlib.cdc import MultiReg
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1515
from .. import *
1616

‎software/glasgow/applet/i2c_master/__init__.py

+1-1
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@@ -1,7 +1,7 @@
11
import argparse
22
import logging
33
import math
4-
from migen import *
4+
from nmigen.compat import *
55

66
from .. import *
77
from ...support.pyrepl import *

‎software/glasgow/applet/jtag/__init__.py

+2-2
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@@ -2,8 +2,8 @@
22
import logging
33
import asyncio
44
from bitarray import bitarray
5-
from migen import *
6-
from migen.genlib.cdc import MultiReg
5+
from nmigen.compat import *
6+
from nmigen.compat.genlib.cdc import MultiReg
77

88
from .. import *
99
from ...support.pyrepl import *

‎software/glasgow/applet/jtag_pinout/__init__.py

+2-2
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@@ -2,8 +2,8 @@
22
import asyncio
33
import random
44
from functools import reduce
5-
from migen import *
6-
from migen.genlib.cdc import MultiReg
5+
from nmigen.compat import *
6+
from nmigen.compat.genlib.cdc import MultiReg
77

88
from .. import *
99
from ...gateware.pads import *

‎software/glasgow/applet/nand_flash/__init__.py

+2-2
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@@ -2,8 +2,8 @@
22
import logging
33
import asyncio
44
import struct
5-
from migen import *
6-
from migen.genlib.cdc import MultiReg
5+
from nmigen.compat import *
6+
from nmigen.compat.genlib.cdc import MultiReg
77

88
from .. import *
99
from ...database.jedec import *

‎software/glasgow/applet/program_ice40/__init__.py

+1-1
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@@ -1,7 +1,7 @@
11
import math
22
import argparse
33
import logging
4-
from migen import *
4+
from nmigen.compat import *
55

66
from .. import *
77

‎software/glasgow/applet/rgb_grabber/__init__.py

+2-2
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@@ -1,7 +1,7 @@
11
import logging
22
import math
3-
from migen import *
4-
from migen.genlib.cdc import *
3+
from nmigen.compat import *
4+
from nmigen.compat.genlib.cdc import *
55

66
from .. import *
77

‎software/glasgow/applet/selftest/__init__.py

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@@ -1,6 +1,6 @@
11
import logging
22
import asyncio
3-
from migen import *
3+
from nmigen.compat import *
44

55
from .. import *
66

‎software/glasgow/applet/shugart_floppy/__init__.py

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@@ -299,8 +299,8 @@
299299
import itertools
300300
import crcmod
301301
import math
302-
from migen import *
303-
from migen.genlib.cdc import MultiReg
302+
from nmigen.compat import *
303+
from nmigen.compat.genlib.cdc import MultiReg
304304

305305
from .. import *
306306
from ...gateware.pads import *

‎software/glasgow/applet/spi_flash_avr/__init__.py

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@@ -5,7 +5,7 @@
55
import asyncio
66
import argparse
77
import collections
8-
from migen import *
8+
from nmigen.compat import *
99
from fx2.format import autodetect, input_data, output_data
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1111
from .. import *

‎software/glasgow/applet/spi_master/__init__.py

+2-2
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@@ -2,8 +2,8 @@
22
import logging
33
import asyncio
44
import math
5-
from migen import *
6-
from migen.genlib.cdc import *
5+
from nmigen.compat import *
6+
from nmigen.compat.genlib.cdc import *
77

88
from .. import *
99

‎software/glasgow/applet/swd/__init__.py

+1-1
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@@ -4,7 +4,7 @@
44
import asyncio
55
import struct
66
import math
7-
from migen import *
7+
from nmigen.compat import *
88

99
from .. import *
1010
from ...gateware.pads import *

‎software/glasgow/applet/uart/__init__.py

+1-1
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@@ -2,7 +2,7 @@
22
import sys
33
import logging
44
import asyncio
5-
from migen import *
5+
from nmigen.compat import *
66

77
from .. import *
88
from ...gateware.pads import *

‎software/glasgow/applet/vga_output/__init__.py

+1-1
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@@ -1,5 +1,5 @@
11
import logging
2-
from migen import *
2+
from nmigen.compat import *
33

44
from .. import *
55
from ...gateware.pads import *

‎software/glasgow/applet/vga_terminal/__init__.py

+1-1
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@@ -2,7 +2,7 @@
22
import asyncio
33
import logging
44
import argparse
5-
from migen import *
5+
from nmigen.compat import *
66

77
from .. import *
88
from ..vga_output import VGAOutputApplet

‎software/glasgow/applet/vga_terminal/cpu.py

+1-1
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@@ -33,7 +33,7 @@
3333
# * JN off ≡ if(A < 0) PC ← PC + signext(off)
3434
# * HLT ≡ halt
3535

36-
from migen import *
36+
from nmigen.compat import *
3737

3838

3939
__all__ = [

‎software/glasgow/gateware/__init__.py

+5-1
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@@ -1,5 +1,9 @@
11
import functools
2-
from migen import *
2+
import os
3+
if os.getenv("NMIGEN"):
4+
from nmigen.compat import run_simulation
5+
else:
6+
from nmigen.compat import run_simulation
37

48

59
__all__ = ["GatewareBuildError", "simulation_test"]

‎software/glasgow/gateware/analyzer.py

+3-4
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
from functools import reduce
22
from collections import OrderedDict
3-
from migen import *
4-
from migen.genlib.fifo import _FIFOInterface, SyncFIFOBuffered
5-
from migen.genlib.coding import PriorityEncoder, PriorityDecoder
3+
from nmigen.compat import *
4+
from nmigen.compat.genlib.fifo import _FIFOInterface, SyncFIFOBuffered
5+
from nmigen.compat.genlib.coding import PriorityEncoder, PriorityDecoder
66

77

88
__all__ = ["EventSource", "EventAnalyzer", "TraceDecodingError", "TraceDecoder"]
@@ -489,7 +489,6 @@ def is_done(self):
489489
# -------------------------------------------------------------------------------------------------
490490

491491
import unittest
492-
from migen.fhdl import verilog
493492

494493
from . import simulation_test
495494

‎software/glasgow/gateware/boneless.py

+8-8
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@@ -1,4 +1,4 @@
1-
from migen import *
1+
from nmigen.compat import *
22

33
from ..arch.boneless.opcode import *
44

@@ -92,7 +92,7 @@ def __init__(self, reset_addr, mem_rdport, mem_wrport, ext_port=None, simulation
9292
ext_port = _StubMemoryPort("ext")
9393

9494
def decode(v):
95-
d = Signal.like(v)
95+
d = Signal.like(v, src_loc_at=1)
9696
self.comb += d.eq(v)
9797
return d
9898

@@ -787,7 +787,7 @@ def test_JSLE(self, tb):
787787
# -------------------------------------------------------------------------------------------------
788788

789789
import argparse
790-
from migen.fhdl import verilog
790+
from nmigen.compat.fhdl import verilog
791791

792792

793793
class BonelessTestbench(Module):
@@ -824,21 +824,21 @@ def __init__(self, has_pins=False):
824824

825825
if args.type == "alu":
826826
tb = _ALU(16)
827-
ios = {tb.s_a, tb.s_b, tb.s_o, tb.c_sel}
827+
ios = (tb.s_a, tb.s_b, tb.s_o, tb.c_sel)
828828

829829
if args.type == "sru":
830830
tb = _SRU(16)
831-
ios = {tb.s_i, tb.s_c, tb.r_o, tb.c_ld, tb.c_dir}
831+
ios = (tb.s_i, tb.s_c, tb.r_o, tb.c_ld, tb.c_dir)
832832

833833
if args.type == "bus":
834834
tb = BonelessTestbench()
835-
ios = {tb.ext_port.adr,
835+
ios = (tb.ext_port.adr,
836836
tb.ext_port.re, tb.ext_port.dat_r,
837-
tb.ext_port.we, tb.ext_port.dat_w}
837+
tb.ext_port.we, tb.ext_port.dat_w)
838838

839839
if args.type == "pins":
840840
tb = BonelessTestbench(has_pins=True)
841-
ios = {tb.pins}
841+
ios = (tb.pins,)
842842

843843
design = verilog.convert(tb, ios=ios, name="boneless")
844844
design.write("boneless.v")

‎software/glasgow/gateware/fx2.py

+4-4
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@@ -23,10 +23,10 @@
2323
# FIFOADR->FLAG 10.7
2424
# FIFOADR->FIFODATA 14.3
2525

26-
from migen import *
27-
from migen.genlib.cdc import MultiReg
28-
from migen.genlib.fifo import _FIFOInterface, AsyncFIFO, SyncFIFO, SyncFIFOBuffered
29-
from migen.genlib.resetsync import AsyncResetSynchronizer
26+
from nmigen.compat import *
27+
from nmigen.compat.genlib.cdc import MultiReg
28+
from nmigen.compat.genlib.fifo import _FIFOInterface, AsyncFIFO, SyncFIFO, SyncFIFOBuffered
29+
from nmigen.compat.genlib.resetsync import AsyncResetSynchronizer
3030

3131

3232
__all__ = ["FX2Arbiter"]

‎software/glasgow/gateware/i2c.py

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@@ -1,7 +1,7 @@
11
# I2C reference: https://www.nxp.com/docs/en/user-guide/UM10204.pdf
22

3-
from migen import *
4-
from migen.genlib.cdc import MultiReg
3+
from nmigen.compat import *
4+
from nmigen.compat.genlib.cdc import MultiReg
55

66

77
__all__ = ['I2CSlave']
@@ -397,7 +397,6 @@ def __init__(self, pads):
397397
# -------------------------------------------------------------------------------------------------
398398

399399
import unittest
400-
from migen.fhdl import verilog
401400

402401
from . import simulation_test
403402

@@ -856,8 +855,3 @@ class _DummyPads(Module):
856855
def __init__(self):
857856
self.scl_t = TSTriple()
858857
self.sda_t = TSTriple()
859-
860-
861-
if __name__ == "__main__":
862-
verilog.convert(I2CMaster(_DummyPads(), 16)).write("i2cmaster.v")
863-
verilog.convert(I2CSlave(_DummyPads())).write("i2cslave.v")

‎software/glasgow/gateware/lfsr.py

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@@ -1,4 +1,4 @@
1-
from migen import *
1+
from nmigen.compat import *
22

33

44
__all__ = ["LinearFeedbackShiftRegister"]
@@ -54,7 +54,6 @@ def generate(self):
5454
# -------------------------------------------------------------------------------------------------
5555

5656
import unittest
57-
from migen.fhdl import verilog
5857

5958
from . import simulation_test
6059

‎software/glasgow/gateware/mpsse.py

+2-13
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@@ -2,8 +2,8 @@
22
# http://www.ftdichip.com/Support/Documents/AppNotes/AN_135_MPSSE_Basics.pdf
33
# http://www.ftdichip.com/Support/Documents/AppNotes/ AN_108_Command_Processor_for_MPSSE_and_MCU_Host_Bus_Emulation_Modes.pdf
44

5-
from migen import *
6-
from migen.genlib.cdc import MultiReg
5+
from nmigen.compat import *
6+
from nmigen.compat.genlib.cdc import MultiReg
77

88

99
__all__ = ['MPSSE']
@@ -427,7 +427,6 @@ def __init__(self, pads):
427427
# -------------------------------------------------------------------------------------------------
428428

429429
import unittest
430-
from migen.fhdl import verilog
431430

432431
from . import simulation_test
433432

@@ -740,13 +739,3 @@ def test_write_single_byte_clkwrong(self, tb):
740739
self.assertEqual((yield from tb.recv_tdi(8, pos=False)), 0xA5)
741740
yield
742741
self.assertEqual((yield tb.tck.o), 0)
743-
744-
745-
if __name__ == "__main__":
746-
tck = TSTriple()
747-
tdi = TSTriple()
748-
tdo = TSTriple()
749-
tms = TSTriple()
750-
engine = MPSSE([tck, tdi, tdo, tms])
751-
752-
verilog.convert(engine).write("mpsse.v")

‎software/glasgow/gateware/pads.py

+2-2
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@@ -1,4 +1,4 @@
1-
from migen import *
1+
from nmigen.compat import *
22

33

44
__all__ = ['Pads']
@@ -82,7 +82,7 @@ def _add_elem(self, elem, name=None, index=None):
8282
# -------------------------------------------------------------------------------------------------
8383

8484
import unittest
85-
from migen.fhdl.specials import Tristate
85+
from nmigen.compat.fhdl.specials import Tristate
8686

8787

8888
class PadsTestCase(unittest.TestCase):

‎software/glasgow/gateware/platform/lattice.py

+1-1
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@@ -1,4 +1,4 @@
1-
from migen import *
1+
from nmigen.compat import *
22

33
from .. import GatewareBuildError
44
from ..pll import PLL

‎software/glasgow/gateware/pll.py

+1-1
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@@ -1,5 +1,5 @@
11
import logging
2-
from migen.fhdl.specials import Special
2+
from nmigen.compat.fhdl.specials import Special
33

44

55
__all__ = ["PLL"]

‎software/glasgow/gateware/registers.py

+1-6
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@@ -1,4 +1,4 @@
1-
from migen import *
1+
from nmigen.compat import *
22

33

44
__all__ = ["Registers", "I2CRegisters"]
@@ -78,7 +78,6 @@ def do_finalize(self):
7878
# -------------------------------------------------------------------------------------------------
7979

8080
import unittest
81-
from migen.fhdl import verilog
8281

8382
from . import simulation_test
8483
from .i2c import I2CSlaveTestbench
@@ -148,7 +147,3 @@ def test_data_read(self, tb):
148147
self.assertEqual((yield from tb.i2c.read_octet()), 0b10100101)
149148
yield from tb.i2c.write_bit(1)
150149
yield from tb.i2c.stop()
151-
152-
153-
if __name__ == "__main__":
154-
verilog.convert(I2CSlave(None)).write("registers.v")

‎software/glasgow/gateware/uart.py

+2-3
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@@ -1,5 +1,5 @@
1-
from migen import *
2-
from migen.genlib.cdc import MultiReg
1+
from nmigen.compat import *
2+
from nmigen.compat.genlib.cdc import MultiReg
33

44

55
__all__ = ['UART', 'uart_bit_cyc']
@@ -292,7 +292,6 @@ def calc_parity(sig, kind):
292292
# -------------------------------------------------------------------------------------------------
293293

294294
import unittest
295-
from migen.fhdl import verilog
296295

297296
from . import simulation_test
298297

‎software/glasgow/platform/__init__.py

+2-2
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@@ -1,5 +1,5 @@
1-
from migen.build.generic_platform import *
2-
from migen.build.lattice import LatticePlatform
1+
from nmigen.compat.build.generic_platform import *
2+
from nmigen.compat.build.lattice import LatticePlatform
33

44
from .programmer import GlasgowProgrammer
55

‎software/glasgow/platform/programmer.py

+1-1
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@@ -1,4 +1,4 @@
1-
from migen.build.generic_programmer import GenericProgrammer
1+
from nmigen.compat.build.generic_programmer import GenericProgrammer
22
from ..device.hardware import GlasgowHardwareDevice
33

44

‎software/glasgow/target/analyzer.py

+3-3
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@@ -1,7 +1,7 @@
11
import logging
2-
from migen import *
3-
from migen.genlib.cdc import MultiReg
4-
from migen.genlib.fifo import _FIFOInterface
2+
from nmigen.compat import *
3+
from nmigen.compat.genlib.cdc import MultiReg
4+
from nmigen.compat.genlib.fifo import _FIFOInterface
55

66
from ..gateware.analyzer import *
77

‎software/glasgow/target/hardware.py

+1-1
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@@ -4,7 +4,7 @@
44
import tempfile
55
import shutil
66
import logging
7-
from migen import *
7+
from nmigen.compat import *
88

99
from ..gateware.pads import Pads
1010
from ..gateware.i2c import I2CSlave

‎software/glasgow/target/simulation.py

+1-1
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@@ -1,4 +1,4 @@
1-
from migen import *
1+
from nmigen.compat import *
22

33
from ..gateware.registers import Registers
44

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